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UPD6345GS 数据表(PDF) 2 Page - NEC |
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UPD6345GS 数据表(HTML) 2 Page - NEC |
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2 / 16 page ![]() µPD6345 2 PIN CONFIGURATION (Top View) PIN IDENTIFICATION Pin No. Symbol Pin name Input/Output Function 1 GND Ground — Connection to Ground (GND) of system. 2 EN Output Enable Input When this pin is low or open, all outputs are OFF, and data is output during high. 3 LAT Latch Enable Input When this pin is low or open, data is latched and data is through to output during high. 4 SO Serial data Output Output Serial data is output on positive-going transition of the clock. In case of connection to cascade additional device ( µPD6345), this pin will be connected to SIN terminal of additional device. 5 to 12 O8 to O1 Driver Output Output High Voltage and Current Driver Outputs. 13 SIN Serial data Input Input Data is loaded to shift register on positive-going transition. 14 SCK Clock Input Data of SIN is loaded to shift register on positive-going transition of SCK. Also, serial data is output from SO on positive-going transition of SCK. 15 RES Reset Input When this pin is low or open, data of shift register is all cleared, and this device operate normally during high. 16 VDD Power Supply — Normally supply 5 V. 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VSS EN LAT SO O8 O7 O6 O5 VDD RES SCK SIN O1 O2 O3 O4 |
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