AN2154

The PWM generator block of ST7MC motor control peripheral for SVPWM

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The PWM generator block of ST7MC motor control

peripheral for SVPWM

This section provides a basic functional description of the 12 bit PWM generator embedded

into the ST7MC motor control peripheral.

Figure 3 schematizes the block diagram of the PWM generator. The 3 PWM signals are

generated using a freerunning 12-bit PWM Counter and three 13-bit Compare registers for

phase U, V and W: MCMPU, MCMPV and MCMPW registers. A fourth 12-bit register

(MCMP0) is needed to set up the PWM carrier frequency. All three PWM signals (Phases U,

V and W) are then directed to the channel manager, in which dead time may be added.

The 12-bit PWM Counter clock is supplied through a 3-bit prescaler to allow the generation

The PWM generator can work in center-aligned or edge-aligned mode, depending on the

CMS bit setting in the MPCR register:

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Center-aligned Mode (CMS bit = 1): In this operating mode, the PWM Counter counts

up to the value loaded in the 12-bit Compare 0 register (MCMP0). Subsequently it

counts down until it reaches zero and restarts counting up. The PWM signals are set to

'0' when the PWM Counter reaches, in counting up, the corresponding 13-bit Compare

register value, and they are set to '1' when the PWM Counter reaches the 13-bit

Compare value again in counting down. Figure 4 shows a center-aligned PWM

waveform, where the Compare 0 register value is equal to 8.

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Edge-aligned Mode (CMS bit = 0): In this operating mode, the PWM Counter counts up

to the value loaded in the 12-bit Compare Register. Then the PWM Counter is cleared

and it restarts counting up. The PWM signals are set to '0' when the PWM Counter

reaches, in counting up, the corresponding 13-bit Compare register value, and they are

waveform, where the Compare 0 register value is equal to 8. Both in center-aligned and

edge-aligned modes, the four Compare registers (one Compare 0 and three for the U,

V and W phases) are updated (and an Update 'U' event interrupt is generated if

enabled) when the PWM counter underflows or overflows, and the 8-bit Repetition

countdown has reached zero.This means that data is transferred from the preload

compare registers to the compare registers every N cycles of the PWM Counter, where

N is the value of the 8-bit Repetition register in edge-aligned mode. When using center-

aligned mode, the repetition countdown is decremented every time the PWM counter

overflows or underflows. Although this limits the maximum number of repetitions to 128

PWM cycles, this makes it possible to update the duty cycle twice per PWM period.