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1 ST72F324 Migration: feature overview

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ST72F324 Migration: feature overview

Table 2.

ST72F324 migration: feature overview

“-” stands for: No change vs. ST72F324, fully compatible with existing development

Note 1: Refer to the corresponding datasheets for more information.

Note 2: Exit from Active Halt available with external interrupts (see Section 7)

Note 3: improved ADC accuracy

Note 4: Go to http://www.st.com for information on third-party tools.

ST72F324

ST72F324B

ST72F325

Package

TQFP44 / SDIP42 /

TQFP32 / SDIP32

--

Program Memory

8 to 32K Flash

-

16 to 32K Flash

Operating Supply

3.8 V to 5.5V

-

-

Register Map

128 bytes

-

-

I/Os (High sink)

32/24 pins

-

-

Power saving Modes

Slow / Wait / Active Halt /

Halt

Nested Interrupts

Yes

-

-

MCC / RTC

Yes

-

-

Watchdog

Yes

-

-

16-bit Timer

(OC / IC / PWM)

2 Timers (3 / 3 / 2)

-

-

8-bit PWMART

(OC / IC / PWM)

No

-

1 Timer

(4 / 0 / 4)

SPI

Yes

-

-

SCI

Yes

-

-

No

-

Yes

ADC

Yes (10-bit)

LVD

3 Levels (No change)

-

-

CSS

No

-

Yes

ICC mode

39-pulse

39-pulse (32k Flash)

36-pulse (8/16k Flash)

39-pulse

Development tools

ST7MDT20x-EMU3 and ST7MTD20-DVP3

ST7232X-SK/RAIS

ST7MDT20x-EPB and ST7MTD20-DVP3