AN2556

New features

21/35

Figure 2.

X-Interrupt basic structure

When different sources submit an interrupt request, the enable bits (Byte High of the

XIRxSEL register) define a mask which controls which sources will be associated with the

unique available vector. If more than one source is enabled to issue the request, the service

routine will have to take care to identify the real event to be serviced. This can easily be

done by checking the flag bits (Byte Low of XIRxSEL register). Note that the flag bit can

provide information about events which are not currently serviced by the interrupt controller

(since masked through the enable bits), allowing an effective software management in the

absence of the possibility to serve the related interrupt request. A period polling of the flag

bits may be implemented inside the user application.

XMISCEN, bit 10 of XPERCON register, must be set to have access to these registers.

Refer to Section 3.1: XPERCON register on page 24 for more details.

Table 13: X-Interrupt detailed mapping gives an overview of the different settings available.

ai13312

70

Flag [7:0]

XIRxSEL[7:0] (x = 0, 1, 2, 3)

XPxIC.IR

(x = 0, 1, 2, 3)

XIRxSEL[15:8] (x = 0, 1, 2, 3)

Enable [7:0]

15

8

IT Source 7

IT Source 6

IT Source 5

IT Source 4

IT Source 3

IT Source 2

IT Source 1

IT Source 0

Table 13.

X-Interrupt detailed mapping

XP0INT

XP1INT

XP2INT

XP3INT

CAN1 Interrupt

X

X

CAN2 Interrupt

X

X

I2C Receive

X

X

X