AN2556

New features

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the enable bit. This AND gate is activated by a transition on the Interrupt source line and not

by the latched value in the XIRxSEL register meaning:

●

A transition on the IT source line will generate an interrupt to the ST10 core if the

source is enabled.

●

Writing to an interrupt request flag in a XIRxSEL register will not generate an interrupt

to the ST10 core.

Example: If XIR0SEL = 0x0100: CAN1 interrupt enabled on XP0IC interrupt.

To trigger by software the CAN1 interrupt routine with the XP0IC register the following code

must be used:

XIR0SET = 0x0001;/* Set CAN1 interrupt request Flag in XIR0SEL */

XP0IC = XP0IC | 0x0080;/* Set XP0IR flag, generate an interrupt */

Executing only the first line will only set the flag in the XIR0SEL register but will not be seen

by the AND gate and cannot set the XP0IR flag.

2.4

Additional ports input control: XPICON register

The possibility to select between TTL and CMOS-like input thresholds has been extended to

the Ports 0, 1 and 5.

2.4.1

Hardware impacts

None.

2.4.2

Software impacts

None.

ST10F273Z4: XPICON (EB26)

XREG

Reset value: --00h

15

14

13

12

11

10

987

65432

10

Reserved

P5H

IN

P5L

IN

P1H

IN

P1L

IN

P0H

IN

P0L

IN

-

RWRWRWRW

RWRW

Table 14.

ST10F273Z4 XPICON register

Bit

Function

Reset value

PxLIN

Port x Low Byte Input Level Selection

0: Pins Px.7..0 switch on standard TTL input levels.

1: Pins Px.7..0 switch on CM0OS input levels

0

PxHIN

Port x High Byte Input Level Selection

0: Pins Px.15..8 switch on standard TTL input levels.

1: Pins Px.15..8 switch on CM0OS input levels.

0