AN2641 datasheet(9/37 Pages) STMICROELECTRONICS

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AN2641

CLCD panel programmable parameters

Doc ID 14027 Rev 1

9/37

When a complete line of pixels is transmitted to the LCD driver, the value in HFP counts

the number of pixel clocks to wait before asserting the line clock. HFP can generate a

period of 1-256 pixel clock cycles.

HSW, 8-bit [15:8] field in the LCD-Timing1 register: specifies the pulse width of the

line clock in passive mode, or the horizontal synchronization pulse in active mode.

PPL, 6-bit [7:2] field in the LCD-Timing1 register: is a value that represents between

16 and 1024 PPL. PPL controls how much data is read from the DMA input buffers

through to the gray-scaler as follows:

Actual pixels-per-line = 16 * (PPL + 1)

The Actual pixels-per-line specifies the number of pixels in each line (or row) of the

screen.

VBP, 8-bit [31:24] field, in the LCD-Timing1 register: specifies the number of line

clocks inserted at the beginning of each frame. The VBP count starts just after the

vertical synchronization signal for the previous frame has been negated for active

mode, or the extra line clocks have been inserted as specified by the VSW bit field in

passive mode. After this has occurred, the count value in VBP sets the number of line

clock periods inserted before the next frame. VBP generates from 0-255 extra line clock

cycles.

VFP, 8-bit [23:16] field, in the LCD-Timing1 register: specifies the number of line

clocks to insert at the end of each frame. When a complete frame of pixels is

transmitted to the LCD display, the value in VFP is used to count the number of line

clock periods to wait.

After the count has elapsed, the CLFP vertical synchronization signal, is asserted in

active mode, or extra line clocks are inserted as specified by the VSW bit-field in

passive mode. VFP generates from G0-255 line clock cycles.

VSW, 6-bit [15:10] field, in the LCD-Timing1 register: specifies the pulse width of the

vertical synchronization pulse. The register is programmed with the number of line

clocks in VSync minus one.

LPP, 10-bit [9:0] field, in the LCD-Timing1 register: specifies the total number of

lines or rows on the LCD panel being controlled. LPP has an allowed range 1-1024

lines. The register is programmed with the number of lines per LCD panel minus 1. For

dual panel displays this register is programmed with the number of lines on each of the

upper and lower panels.

2.2

Panel clock source and frequency

CLCD_CLK is a free running reference clock (currently 48 MHz), which drives the CLCD

controller.

CLCP, the output of the panel clock generator, is the CLCD panel clock frequency which

goes from the CLCD controller to the CLCD panel. CLCP can be programmed in the range

from CLCD_CLK/2 to CLCD_CLK/33 to match the BPP data rate of the LCD panel.

If the CLCD panel requires a frequency outside this range (CLCD_CLK/2 to

CLCD_CLK/33), then an alternative route is to use another clock source (for example PLL2

or AHB) instead of CLCD_CLK and use a prescaler to obtain the desired frequency.

●

One choice is to select the AHB as input clock. This can be done just using software

modifications. You can select the AHB clock source using the CLKSEL bit and can

divide the AHB frequency using the PCD bits. All these registers are described in the

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