AN2641

CLCD controller dataflow

Doc ID 14027 Rev 1

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CLCD controller dataflow

Packets of pixel-coded data are first stored in memory (frame buffer). Then, they are fed, via

the AHB interface, to dual 16-deep 32 bit-wide DMA FIFO, both of which act as input data

flow buffers. The buffered pixel-coded data is then unpacked via a pixel serializer.

Depending on the LCD type and mode, the unpacked data may represent:

●

an actual true display gray or color value or

●

an address in a 256 x 16 bit wide palette RAM containing a gray or color value

In the case of STN displays, either a palette value or the true value is passed to the gray

scaling generators. The hardware coded gray scale algorithm logic sequences the

addressed pixels activity over a programmed number of frames to provide the effective

display appearance.

For TFT display, either an addressed palette value or true color value is passed directly to

the output display drivers.

Figure 4.

Data flow in CLCD controller

Figure 4 shows the Data Flow in the respective hardware blocks. There are 2 decision

boxes.

First decision box - using the palette RAM:

●

Dependent upon the LCD type and code, the unpacked data may represent:

–

An actual true display gray or color value (16 BPP or higher) or

–

An address to a 256 x 16 bit wide palette RAM gray or color value (1, 2, 4 or 8

BPP)

●

Palette use is linked to display type and mode. A palette is used by:

–

Mono STN displays with 1, 2 or 4 BPP

–

Color STN or TFT displays with 1, 2, 4, 8 BPP

Otherwise, non-palettized true-color is used.

Second decision box - using the grey scaling algorithm:

●

In the case of STN displays, either a palette value or the true value is passed to the

gray scaling generators. The hardware coded grey scale algorithm logic sequences the

FIFO

CTR

UP

DMA

FIFO

LP

DMA

FIFO

PIXEL

SERIALIZER

PALETTE

GREY

SCALING

ALGO

UPPER

PANEL

OUTPUT

FIFO

LOWER

PANEL

OUTPUT

FIFO

STN/TFT

DATA

SELECT

FRAME

BUFFER

LCD

PANEL