AN3202

Summary

Doc ID 17399 Rev 1

9/11

5

Summary

A general purpose timer can be seen as a simple counter with two clocks in input:

READ_Clk (for the slave interface) and CNT_Clk (for incrementing/decrementing the

counter).

The CNT_Clk for the GPT in SPEAr600 can be selected between a fixed 48 MHz source

and PLL1, which is also the source clock for the rest of the system. The READ_Clk is

derived from PLL1 in normal mode (PCLK) and from the 30 MHz OSCI in slow mode.

Having a fixed clock source different from the system clock has the advantage of eliminating

the need for reconfiguring the GPT registers if the system clock frequency is slowed down.

However, it introduces the possibility of obtaining an unpredictable result when reading the

timer value, due to the non-synchronous operation of the two clocks.

In case CNT_Clk is much slower than READ_Clk, three consecutives read of the counter (3-

reads workaround) guarantees to have at least two stable values with a maximum difference

of 1.

The following table summarizes the suggested solutions for this issue:

Table 3.

Summary of the solutions

Subsystem

Solution in normal mode

Solution in slow mode

GPT1

ARM1

3-reads workaround

3-reads workaround

GPT2

ARM2

3-reads workaround

3-reads workaround

GPT3

Basic

3-reads workaround

3-reads workaround

GPT4

Application1

Keep READ_Clk and

CNT_Clk synchronous

3-reads workaround

GPT5

Application2

Keep READ_Clk and

CNT_Clk synchronous

3-reads workaround