AN3202

General purpose timers (GPTs) in SPEAr600

Doc ID 17399 Rev 1

3/11

1

General purpose timers (GPTs) in SPEAr600

In the SPEAr600 architecture, there are five different GPT blocks located in the various

subsystems. Each timer block consists of two independent channels, each one with a 16-bit

counter register.

Table 1.

GPTs in SPEAr600

Each timer has a READ_Clk, input which is the APB clock (PCLK), and a CNT_Clk, which

can be selected by the user from a list of clock sources.

●

READ_Clk (PCLK): When SPEAr600 is in normal mode, it takes the input from PLL1

divided by a programmable prescaler, whose reset values impose the ratio 1:2:4 to the

core_clk, HCLK and PCLK clocks. When SPEAr600 is in slow mode, it takes directly

the input from the OSCI signal.

●

CNT_Clk: The clock source can be selected as either a fixed 48 MHz or the PLL1 itself

divided by a programmable prescaler, which is defined in the PRSC1_CLK_CFG

register (0xFCA8_0044) for GPT1/GPT2/GPT3, PRSC2_CLK_CFG register

(0xFCA8_0048) for GPT4 and PRSC3_CLK_CFG register (0xFCA8_004C) for GPT5.

The CNT_Clk may then be further divided by a GPT internal 4-bit prescaler able to

divide up to 256 times (‘/256’).

Figure 1.

GPT clock sources

The following table describes the clock selectors (Clock_Sel) for each GPT.

Subsystem

Base address

GPT1

ARM1

0xF000_0000

GPT2

ARM2

0xF000_0000

GPT3

Basic

0xFC80_0000

GPT4

Application 1

0xD800_0000

GPT5

Application 2

0xD808_0000

GPT Ch1

GPT Ch2

Read_CLK

(PCLK)

CNT_Clk

PLL3 (48MHz)

PRSCx_CLK_CFG

PLL1 (332MHz)/

OSCI (24MHz)

HCLK/PCLK

prescaler

MUX

PLL1 (332MHz)

Clock_Sel

int_prsc