AN3206

Reference design

Doc ID 17406 Rev 3

5/14

would yield higher signal voltage swings at the LNA input, making the input referred noise

less significant and thereby improving sensitivity. However, this also increases the source

resistance, thereby increasing the source noise voltage. In practice at the 700

Ω level, the

improvement gradient is very small and the transmit output power exhibits far greater

sensitivity to load variation than receiver sensitivity. The main objective for receive sensitivity

is to minimize network loss, which is a common objective when transmitting.

The optimum load presented to the pins of the STM32W108 device must take into

consideration not only the optimum PA load but also on-chip parasitic capacitance and

package bond-wire inductance. It is estimated that the optimum load presented to the pins is

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Ω (series impedance). This is equivalent to a parallel resistance of 368Ω combined

with a parallel inductance of 6.6 nH.

2.1.3

Matching network circuit design

The term “matching” typically implies conjugate power matching. It is important to

understand that the STM32W PA is not power matched according to the traditional

definition. The term is used in this document to describe the design of an optimal PA

impedance.

The best way to understand ST's approach towards optimizing the STM32W “matching” is to

plot on the Smith chart the impedance of the ideal 700

Ω PA load transformed by the

chip/package parasitic elements. The combination of the ideal load with the parasitic

elements is the conjugate of the ideal load presented to the package pins. Knowing the

combined load and its conjugate allows the designer to approach matching in a more

traditional sense, namely, “How do we get to 50

Ω?”

It is also necessary at some point in the network to include a balanced-to-unbalanced

(balun) conversion. Use of a ‘proper’ balun has performance benefits related to common-

mode suppression both on transmit and receive sides.

There are a variety of balun architectures and solutions available. The primary objective of

any of ST's reference designs is to minimize design complexity and maximize time to

market. Therefore, ST decided to implement its primary reference design with a ceramic

balun. The cost of ceramic baluns is low, and they are available from a number of vendors.

Ceramic baluns are available in 1:1 (50 to 50

Ω), 2:1 (100 to 50Ω), and 4:1 ratios (200 to

50

Ω).

The magnitude of the reflection coefficient, |

⎡

●

1:1 (50

Ω) → 0.8

●

2:1 (100

Ω) → 0.76

●

4:1 (200

Ω) → 0.8

This implies that a 2:1 ceramic balun should offer the lowest network loss, assuming

identical balun loss because it requires the least transformation.

Investigation into ceramic balun performance from various vendors reveals that 1:1 and 2:1

ratio baluns often have an approximate 0.3 dB insertion loss advantage over a 4:1 ratio.

Thus the use of a 2:1 ceramic balun is preferred.

Optimal Load for STM32W (series impedance)

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Ohms