AN3427 datasheet(23/52 Pages) STMICROELECTRONICS

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AN3427

Peripheral migration

Doc ID 019001 Rev 1

23/52

3.5

DMA

STM32 F2 series features a new DMA controller specially designed to get optimum system

bandwidth, based on a complex bus matrix architecture. Thus the architecture, features and

registers of this controller are different from the DMA embedded in the F1 series, i.e. any

code on F1series using the DMA needs to be rewritten to run on F2 series.

STM32 F1 series embeds two DMA controllers, each controller has up to 7 channels. Each

channel is dedicated to managing memory access requests from one or more peripherals. It

has an arbiter for handling the priority between DMA requests.

STM32 F2 series embeds two DMA controllers, each controller has 8 streams, each stream

is dedicated to managing memory access requests from one or more peripherals. Each

stream can have up to 8 channels (requests) in total. Each has an arbiter for handling the

priority between DMA requests.

The table below presents the correspondence between peripheral’s DMA requests in

STM32 F1 series and STM32 F2 series.

For more information about STM32 F2’s DMA configuration and usage, please refer to

section "Stream configuration procedure" in DMA chapter of STM32F2xx Reference Manual

(RM0033).

Table 7.

DMA request differences between STM32 F1 series and STM32 F2 series

Peripheral

DMA request

STM32 F1series

STM32 F2 series

ADC1

DMA1_Channel1

DMA2_Channel0: stream0 / stream4

ADC2

DMA2_Channel1: stream2 / stream3

ADC3

DMA2_Channel5

DMA2_Channel2: stream0 / stream1

DAC

DAC_Channel1

DAC_Channel2

DMA2_Channel3 / DMA1_Channel3(1)

DMA2_Channel4 / DMA1_Channel4(1)

DMA1_Channel7: stream5

DMA1_Channel7: stream6

SPI1

SPI1_Rx

SPI1_Tx

DMA1_Channel2

DMA1_Channel3

DMA2_Channel3: stream0 / stream2

DMA2_Channel3: stream3 / stream5

SPI2

SPI2_Rx

SPI2_Tx

DMA1_Channel4

DMA1_Channel5

DMA1_Channel0: stream3

DMA1_Channel0: stream4

SPI3

SPI3_Rx

SPI3_Tx

DMA2_Channel1

DMA2_Channel2

DMA1_Channel0: stream0 / stream2

DMA1_Channel0: stream5 / stream7

USART1

USART1_Rx

USART1_Tx

DMA1_Channel5

DMA1_Channel4

DMA2_Channel4: stream2 / stream5

DMA2_Channel4: stream7

USART2

USART2_Rx

USART2_Tx

DMA1_Channe6

DMA1_Channel7

DMA1_Channel4: stream5

DMA1_Channel4: stream6

USART3

USART3_Rx

USART3_Tx

DMA1_Channe3

DMA1_Channel2

DMA1_Channel4: stream1

DMA1_Channel4: stream3 /

DMA1_Channel7: stream4

USART6

USART6_Rx

USART6_Tx

DMA2_Channel5: stream1 / stream2

DMA2_Channel5: stream6 / stream7

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