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AN4031

DMA controller description

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1.1.10

Source and destination burst size

Burst transfers are guaranteed by the implemented DMA FIFOs.

Figure 5. DMA burst transfer

In response to a burst request from peripheral DMA reads/writes the number of data units

(data unit can be a word, a half-word, or a byte) programmed by the burst size (4x, 8x or 16x

data unit). The burst size on the DMA peripheral port must be set according to the peripheral

needs/capabilities.

The DMA burst size on the memory port and the FIFO threshold configuration must match.

This allows the DMA stream to have enough data in the FIFO when burst transfer on the

memory port is started. Table 6 shows the possible combinations of memory burst size,

FIFO threshold configuration and data size.

To ensure data coherence, each group of transfers that form a burst is indivisible: AHB

transfers are locked and the arbiter of the AHB bus matrix does not remove the DMA

master’s access rights during the burst transfer sequence.