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AN4031

System performance considerations

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Figure 10. DMA transfer delay due to CPU transfer issued by interrupt

The above figure details the case of a DMA transfer delayed by a CPU multi-cycle transfer

due to an interrupt entry. DMA memory port is triggered to perform a memory access. After

arbitration, AHB bus is not granted to DMA1 memory port but to CPU System Bus. An

additional delay is observed to serve the DMA request. It is 8 AHB cycles for a CPU transfer

issued by interrupt.

The same behavior can be observed with other masters (like DMA2, USB_HS, Ethernet…)

when addressing simultaneously the same slave with a transaction length different from one

data unit.

In order to improve DMA access performance over BusMatrix, it is recommended to avoid

bus contention.

2.2

DMA transfer paths

2.2.1

Dual DMA port

STM32F2/F4 devices embed two DMAs. Each DMA has two ports, a memory port and a

peripheral port, which can operate simultaneously not only at DMA level but also with other

system masters, using the external bus matrix and dedicated DMA paths.

The simultaneous operation allows to optimize DMA efficiency and to reduce response time

(wait time between request and data transfer).