DocID023035 Rev 4

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AN4080

Power supplies and reset sources of the STM32F0xx family

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Low-power mode security reset

To prevent that critical applications mistakenly enter a low-power mode, two low-power

mode security resets are available. If enabled in Option bytes, the resets are generated in

the following conditions:

1.

Entering Standby mode: this type of reset is enabled by resetting nRST_STDBY bit in

User Option Bytes. In this case, whenever a Standby mode entry sequence is

successfully executed, the device is reset instead of entering Standby mode.

2.

Entering Stop mode: this type of reset is enabled by resetting nRST_STOP bit in User

Option Bytes. In this case, whenever a Stop mode entry sequence is successfully

executed, the device is reset instead of entering Stop mode.

Caution:

In the STM32F0x8 devices, the voltage regulator is bypassed, therefore the standby mode

is not available.

Option byte loader reset

The option byte loader reset is generated when OBL_LAUNCH (bit 13) is set in the

FLASH_CR register. This bit launches the option byte loading by software.

Power reset

A power reset sets all registers to their reset values, except the RTC domain.

In the STM32F0x1/x2 devices, the power reset is generated when one of the following

events occurs.

1.

Power-on/power-down reset (POR/PDR reset)

2.

Exiting Standby mode

For the STM32F0x8 devices, the Power-on reset must be provided externally. It is

generated while the NPOR pin is low. For more information concerning NPOR, see

Section 1.2.2: External power-on reset and power-down reset (NPOR) of the STM32F0x8

devices.

RTC domain reset

The RTC domain reset only affects the RTC, LSE, LSI and the backup registers. It is

generated when one of the following events occurs.

1.

Software reset, triggered by setting the BDRST bit in the RTC domain control register

(RCC_BDCR).

2.