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AN4080 数据表(PDF) 23 Page - STMicroelectronics |
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AN4080 数据表(HTML) 23 Page - STMicroelectronics |
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23 / 35 page ![]() DocID023035 Rev 4 23/35 AN4080 Debug management 34 4.3.2 SWD pin assignment After reset (SYSRESETn or PORESETn), the pins used for the SWD are assigned as dedicated pins which are immediately usable by the debugger host. However, the MCU offers the possibility to disable the SWD, therefore releasing the associated pins for general-purpose I/O (GPIO) usage. For more details on how to disable SWD port, refer to the RM0091 section on I/O pin alternate function multiplexer and mapping. 4.3.3 Internal pull-up and pull-down on SWD pins Once the SWD I/O is released by the user software, the GPIO controller takes control of these pins. The reset states of the GPIO control registers put the I/Os in the equivalent states: • SWDIO: alternate function pull-up • SWCLK: alternate function pull-down Having embedded pull-up and pull-down resistors removes the need to add external resistors. 4.3.4 SWD port connection with standard SWD connector Figure 9 shows the connection between the STM32F0xx and a standard SWD connector. Figure 9. SWD port connection Caution: In STM32F07x/04x devices, the SWCLK and SWDIO pins are supplied by the VDDIO2 domain. Therefore, you must provide VDDIO2 supply instead of VDD to the SWD connector in order to ensure correct behavior of the debugger tool. |
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