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LTC1153 数据表(PDF) 9 Page - Linear Technology |
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LTC1153 数据表(HTML) 9 Page - Linear Technology |
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9 / 16 page ![]() 9 LTC1153 should be connected across the load, as shown in Figure 2, to safely divert the stored energy. Capacitive Loads Large capacitive loads, such as complex electrical sys- tems with large bypass capacitors, should be powered using the circuit shown in Figure 3. The gate drive to the power MOSFET switch is passed through an RC delay network, R1 and C1, which greatly reduces the turn on ramp rate of the switch. And since the MOSFET source voltage follows the gate voltage, the load is powered smoothly and slowly from ground. This dramatically re- duces the start-up current flowing into the supply capaci- tor/s which, in turn, reduces supply transients and allows for slower activation of sensitive electrical loads. (Diode, D1, provides a direct path for the LTC1153 protection circuitry to quickly discharge the gate). S APPLICATI I FOR ATIO Using the values shown in Figure 3, the start-up current is less than 100mA and does not false-trip the breaker. Lamp Loads The inrush current created by a lamp during turn-on can be 10 to 20 times greater than the rated operating current. The circuit shown in Figure 4 shifts the trip threshold up by a factor of 11:1 (to 30A) for 100ms while the bulb is turned on. The trip threshold then drops down to 2.7A after the inrush current has subsided. The RC network, RD and CD, in series with the drain sense input should be set to trip based on the expected charac- teristics of the load after start-up. With this circuit, it is possible to power a large capacitive load and still react quickly (10 µs) to break the circuit if a short-circuit condi- tion is encountered. The ramp rate at the output of the switch as it lifts off ground is approximately: dV/dt = (VGATE – VTH)/(R1 × C1) And therefore the current flowing into the capacitor during start-up is approximately: ISTART-UP = CLOAD × dV/dt BREAKER CURRENT (1 = SET CURRENT) 1 0.01 10 10 100 LTC1153 • F05 1 0.1 Figure 5. Trip Delay Time vs Breaker Current Selecting RD and CD Figure 5 is a graph of normalized breaker trip time versus breaker current. This graph is used to select the two delay components, RD and CD, which make up a simple RC delay between the drain sense resistor and the drain sense input. Figure 3. Powering Large Capacitive Loads IN CT STATUS GND VS DS G SD LTC1153 CT 0.47 µF + 470 µF MTP3055E 15V 12V 0.036 Ω LTC1153 • F03 CD 0.01 µF RD 1OOk R1 1OOk R2 1OOk D1 1N4148 C1 0.33 µF + CLOAD 100 µF OUT IN CT STATUS GND VS DS G SD LTC1153 CT 0.33 µF + 470 µF MTP3055EL 9.1V 12V 0.036 Ω LTC1153 • F04 10k 1M 0.1 µF VN2222LL 100k 12V/1A BULB Figure 4. Lamp Driver with Delayed Protection |
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