DocID027335 Rev 2

9/19

AN4640

Peripherals interconnect matrix

18

2.1

Timers block

2.1.1

From TIM to TIM

Some of the timers are linked together internally for synchronization or chaining. When one

timer is configured in Master mode, it can reset, start, stop or clock the counter of another

timer configured in Slave mode.

A description of this feature is provided in the “Timer synchronization” section of RM0390

and RM0090 reference manuals, while all the possible master/slave connections are

described in the “TIMx internal trigger connection” tables of the same documents.

The output (from Master) is on signal TIMx_TRGO following a configurable timer event. The

input (to slave) is on signals TIMx_ITR0/ITR1/ITR2/ITR3.

Figure 2 is an overview of the trigger selection and the Master mode selection blocks.

Figure 2. Master / Slave timer overview

VBAT

----

---

---

-

X

-

---

VREFIN

----

---

---

-

X

-

---

EXTI

----

---

---

-

X

X

X

X

X

1. Not in STM32F446xx.

2. Only in STM32F446xx.

3. Available only in STM32F42xxx. STM32F43xxx and STM32F446xx.

4. Available only in STM32F42xxx and STM32F43xxx.

Users

Timers

DMA

Analog

Generators

ADC

DAC

1

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