DocID027483 Rev 1

9/21

AN4655

SW methods

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functions to configure a dedicated peripheral, to perform single read and write operations, or

to open and close communication sessions. The process events are normally handled by

callbacks performing the correct flow of data or occasional error states. Universality pains

here again and the task can be simplified considerably when some functionality can be

limited or even removed and not supported. Big advantage of this method is better code

readability while the code can remain well structured. Drawbacks are time and performance

constraints.

2.2

Applicable methods

Two basic methods can be applied when emulating a communication peripheral by SW:

1.

bit banging;

2.

a combination of HW and SW control of GPIOs.

2.2.1

Bit banging

Signals are emulated by direct control of IO ports via SW purely. This method can be used

at synchronous protocols especially (SPI, I2C) where signal timing usually isn’t so critical.

SPI bit-banging sequence and I2C master bit-banging sequence indicate possible solutions.

2.2.2

Combination of HW and SW control of GPIOs

Signals are emulated indirectly while using capability of specific HW to control IOs at

required times. The communication logic is then implemented at software level, mostly at

interrupt services driven from the internal HW events. User can study the principle in UART

duplex channel based on combination of HW and SW control of GPIOs, demonstrating the

application of this method in a real case.

The user can find another possible solution in already cited AN4457.

This document describes in detail HW synchronization between timers and DMA: events

from a dedicated timer synchronize and trigger sequences of DMA transfers between a

specific data buffer and GPIO registers. Content of data buffer can be either source of GPIO

output control sequence stored in advance by SW in a a dedicated memory area, or a

sequence of samples read and stored from GPIO input to be analyzed after the closing of

the transaction. These transfers are provided at exact intervals during communication

transactions, while a simultaneous flow in both direction can proceed under independent

control.

2.3

Common principles of the methodology

2.3.1

Master vs. slave, clock signal aspects

Master emulation is an easier case in principle. It can determine time slot flow

communication, data flow can be handled off line (e.g. CRC calculation can be prepared in

advance and checked afterwards over the data package) so the physical data flow can be

handled in a relatively fast way.

Master providing synchronous clock is the simplest case. Master starts the flow, handles

clock & data signal, timing is not crucial here and it is nearly free except some if some