DocID027483 Rev 1

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AN4655

SW methods

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2.5

Examples

2.5.1

UART duplex channel based on combination of HW and SW control

of GPIOs

This example shows how to control both transmit and receive processes by software, based

on HW events.

Overflow and IO capture events of a single Capture & Compare timer is used to control

timing of emulation of UART input sampling and output handling of the Rx and Tx signals.

The associated input capture pin is dedicated to receive data. Any general-purpose output

pin or associated output compare pin can be used for data transmission. The timer overflow

period is set to the channel half bit rate by setting the timer auto reload register. Figure 3

illustrates the timing diagram.

Figure 3. UART duplex channel based on timer capture events

Transmission process control is based on regular interrupts from the timer overflow events.

After data for transmission is stored into dedicated variable (transmit buffer simulated by

SW), an internal transmission request appears and the nearest overflow interrupt is used to

start a new transmission (maximum latency for transmission start could be half a bit period).

This is because the same timer is used for control both transmit and receive processes not

synchronized normally. Every even timer overflow event interrupt controls the consecutive

edge changes of the transmitted signal on the dedicated output pin until the end of the frame

transmission. Odd overflow interrupts are discarded.

The receive process uses both input capture and output compare feature of the same timer

and its dedicated pin. Initially, the input capture is performed at the pin. After detecting the

first falling edge, the value captured in the capture register is then used for compare

purposes because the input pin functionality is switched to output compare mode (without

affecting any output GPIO capability since the pin still stays in input mode). Due to the half-

a-bit overflow period of the timer, the nearest output compare event points to the middle of

the first receive bit (start bit). Sampling can be simulated by three consecutive reading of the

input pin level at that moment and if, for each of them, a low level is detected, the correctly

received start bit is evaluated. The receive process then continues by watching every next

odd output compare event. The same three point sampling method can be performed with

noise detection logic here and for all the other received data bits until the end of the current