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AN4661

Debug management

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5

Debug management

5.1

Introduction

The host/target interface is the hardware equipment that connects the host to the application

board. This interface is made of three components: a hardware debug tool, a JTAG or SW

connector and a cable connecting the host to the debug tool. Figure 13 shows the

connection of the host to the evaluation board.

Figure 13. Host to board connection

5.2

SWJ debug port (serial wire and JTAG)

The core of the STM32F746xx/STM32F756xx integrates the Serial Wire / JTAG Debug Port

interface and a SW-DP (2-pin) interface.

•

The JTAG Debug Port (JTAG-DP) provides a 5-pin standard JTAG interface to the

AHP-AP port.

•

The Serial Wire Debug Port (SW-DP) provides a 2-pin (clock + data) interface to the

AHP-AP port.

In the SWJ-DP, the two JTAG pins of the SW-DP are multiplexed with some of the five JTAG

pins of the JTAG-DP.

For more details on the SWJ debug port refer to RM0385 SWJ debug port section (serial

wire and JTAG).

5.3

Pinout and debug port pins

The STM32F746xx/STM32F756xx devices are available in various packages with different

numbers of available pins. As a result, some functionality related to pin availability (TPIU

parallel output interface) may differ between packages.