DocID027559 Rev 1

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AN4661

Debug management

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5.3.3

Internal pull-up and pull-down on JTAG pins

It is necessary to ensure that the JTAG input pins are not floating since they are directly

connected to flip-flops to control the debug mode features. A special care must be taken

with the SWCLK/TCK pin which is directly connected to the clock of some of these flip-flops.

To avoid any uncontrolled IO levels, the device embeds internal pull-ups and pull-downs on

the JTAG input pins:

•

NJTRST: Internal pull-up.

•

JTDI: Internal pull-up.

•

JTMS/SWDIO: Internal pull-up.

•

TCK/SWCLK: Internal pull-down.

Once a JTAG IO is released by the user software, the GPIO controller takes control again.

The reset states of the GPIO control registers put the I/Os in the equivalent state:

•

NJTRST: AF input pull-up.

•

JTDI: AF input pull-up.

•

JTMS/SWDIO: AF input pull-up.

•

JTCK/SWCLK: AF input pull-down.

•

JTDO: AF output floating.

The software can then use these I/Os as standard GPIOs.

Note:

The JTAG IEEE standard recommends to add pull-ups on TDI, TMS and nTRST but there is

no special recommendation for TCK. However, for JTCK, the device needs an integrated

pull-down.

Having embedded pull-ups and pull-downs removes the need to add external resistors.

5.3.4

SWJ debug port connection with standard JTAG connector

Figure 14 shows the connection between the STM32F7xxxx and a standard JTAG

connector.

Figure 14. JTAG connector implementation