9

LTC1065

S

APPLICATI

I FOR ATIO

CLOCK FREQUENCY (kHz)

0

4

3

2

1

0

–1

–2

–3

–4

400

1065 F05

100

200

300

500

C = 200pF

CLOCK FREQUENCY (MHz)

0.5

0.80

0.75

0.70

0.65

0.60

0.55

0.50

0.45

0.40

2.5

1065 F06

1.0

1.5

2.0

3.0

C = 10pF

CLOCK FREQUENCY (MHz)

0.5

0.80

0.75

0.70

0.65

0.60

0.55

0.50

0.45

0.40

2.5

1065 F07

1.0

1.5

2.0

3.0

C = 10pF

A 4pF parasitic capacitance is assumed in parallel with the

external 10pF capacitor. A

±1% clock frequency variation

from device to device can be expected. The 2MHz clock

frequency designed above will typically drift to 1.74MHz at

70

°C (Figure 7).

The internal clock of the LTC1065 can be overridden by an

external clock provided that the external clock source can

drive the timing capacitor C, which is connected from the

clock input pin to ground.

Output Offset

The DC output offset of the LTC1065 is trimmed to

typically less than

±5V.ToobtainoptimumDCoffsetperformance,appropri-

ate PC layout techniques should be used and the filter IC

should be soldered to the PC board. A socket will degrade

the output DC offset by typically 1mV. The output DC offset

is sensitive to the coupling of the clock output pin 4 (N

package) to the negative power supply pin 3 (N package).

The negative supply pin should be well decoupled. When

the surface mount package is used, all NC pins should be

grounded. When the output DC voltage is measured with

a voltmeter, the filter output pin should be buffered. Long

test leads should be avoided.

With fixed power supplies, the output DC offset should not

change by more than

±100µV over 10Hz to 1MHz clock

frequency variation. When the filter clock frequency is

fixed, the output DC offset will typically change by – 4mV

(2mV) when the power supply varies from

±5V to ±7.5V

(

±2.5V). See Typical Performance Characteristics.

Common-Mode Rejection

The common-mode rejection is defined as the change of

the output DC offset with respect to the DC change of the

input voltage applied to the filter.

CMR = 20log (

Table 3 illustrates the common-mode rejection for three

power supplies and three temperatures. The common-

mode rejection improves if the output offset is adjusted to

approximately 0V. The output offset can be adjusted via

pin 8 (N package). See Typical Applications.