LTC1090CSW datasheet(21/28 Pages) LINER

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LTC1090

1090fc

MUX address bit is shifted in and continues during the

remainder of the data transfer. On the falling edge of the

final SCLK, the S&H goes into hold mode and the conver-

sion begins. The voltage will be held on either the 8th,

10th, 12th or 16th falling edge of the SCLK depending on

the word length selected.

Differential Inputs

With differential inputs or when the COM pin is not tied to

ground, the A/D no longer converts just a single voltage

but rather the difference between two voltages. In these

cases, the voltage on the selected “+” input is still sampled

and held and therefore may be rapidly time varying just as

in single ended mode. However, the voltage on the se-

lected “–” input must remain constant and be free of noise

and ripple throughout the conversion time. Otherwise, the

differencing operation may not be performed accurately.

The conversion time is 44 ACLK cycles. Therefore, a

change in the “–” input voltage during this interval can

“–” input this error would be:

VERROR (MAX) = VPEAK x 2 x π x f(“–”) x 44/fACLK

Where f(“–”) is the frequency of the “–” input voltage,

VPEAK is its peak amplitude and fACLK is the frequency of

the ACLK. In most cases VERROR will not be significant. For

a 60Hz signal on the “–” input to generate a 1/4LSB error

(1.25mV) with the converter running at ACLK = 2MHz, its

peak value would have to be 150mV.

5. Reference Inputs

The voltage between the reference inputs of the LTC1090

defines the voltage span of the A/D converter. The refer-

ence inputs look primarily like a 10kΩ resistor but will

have transient capacitive switching currents due to the

switched capacitor conversion technique (see Figure 14).

During each bit test of the conversion (every 4 ACLK

cycles), a capacitive current spike will be generated on the

reference pins by the A/D. These current spikes settle

quickly and do not cause a problem. However, if slow

settling circuitry is used to drive the reference inputs, care

must be taken to insure that transients caused by these

current spikes settle completely during each bit test of the

conversion.

When driving the reference inputs, three things should be

kept in mind:

1. The source resistance (ROUT) driving the reference

inputs should be low (less than 1Ω) to prevent DC

drops caused by the 1mA maximum reference current

(IREF).

2. Transients on the reference inputs caused by the

capacitive switching currents must settle completely

during each bit test (each 4 ACLK cycles). Figures 15

and 16 show examples of both adequate and poor

settling. Using a slower ACLK will allow more time for

the reference to settle. However, even at the maximum

ACLK rate of 2MHz most references and op amps can

be made to settle within the 2µs bit time.

3. It is recommended that the REF– input be tied directly

to the analog ground plane. If REF– is biased at a voltage

other than ground, the voltage must not change during

a conversion cycle. This voltage must also be free of

noise and ripple with respect to analog ground.

Figure 14. Reference Input Equivalent Circuit

Figure 15. Adequate Reference Settling

HORIZONTAL: 1µs/DIV

APPLICATIO S I FOR ATIO

LTC1090 • AI19

ROUT

REF +

REF –

VREF

EVERY 4 ACLK CYCLES

10k

TYP

RON

5pF – 30pF

LTC1090

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