LTC1553_15 datasheet(18/24 Pages) LINER

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LTC1553

APPLICATIONS INFORMATION

the suggested values slightly because of board layout and

operating condition differences.

An alternate output capacitor is the Sanyo MV-GX series.

Using multiple parallel 1500

µF Sanyo MV-GX capacitors

for the output capacitor, Table 8 shows the suggested

compensation component value for a 5V input application

based on the inductor and output capacitor values.

Table 8. Suggested Compensation Network for 5V Input

Application Using Multiple Paralleled 1500

µF SANYO MV-GX

Output Capacitors

LO (µH)

CO (µF)

RC (kΩ)CC (µF)

C1 (pF)

4500

4.3

0.022

270

6000

5.6

0.0047

220

9000

8.2

0.01

150

2.7

4500

0.01

100

2.7

6000

0.01

2.7

9000

0.01

5.6

4500

0.01

5.6

6000

0.0047

5.6

9000

0.0047

VID0 to VID4, PWRGD and FAULT

The digital inputs (VID0 to VID4) program the internal DAC

which in turn controls the output voltage. These digital

input controls are intended to be static and are not

designed for high speed switching. Forcing VOUT to step

from a high to a low voltage by changing the VIDn pins

quickly can cause FAULT to trip.

Figure 11 shows the relationship between the VOUT volt-

age, PWRGD and FAULT. To prevent PWRGD from inter-

rupting the CPU unnecessarily, the LTC1553 has a built-in

tPWRBAD delay to prevent noise at the SENSE pin from

toggling PWRGD. The internal time delay is designed to

take about 500

µs for PWRGD to go low and 1ms for it to

recover. Once PWRGD goes low, the internal circuitry

watches for the output voltage to exceed 115% of the rated

voltage. If this happens, FAULT will be triggered. Once

FAULT is triggered, G1 and G2 will be forced low immedi-

ately and the LTC1553 will remain in this state until VCC

power supply is recycled or OUTEN is toggled.

complication of input and/or output filters, unknown

capacitor ESR, and gross operating point changes with

input voltage, load current variations, all suggest a more

practical empirical method. This can be done by injecting

a transient current at the load and using an RC network box

to iterate toward the final compensation values, or by

obtaining the optimum loop response using a network

analyzer to find the actual loop poles and zeros.

Table 6. Suggested Compensation Network for 5V Input

Application Using Multiple Paralleled 330

µF AVX TPS Output

Capacitors

LO (µH)

CO (µF)

RC (kΩ)CC (µF)

C1 (pF)

990

1.8

0.022

680

1980

3.6

0.01

330

4950

9.1

0.01

120

2.7

990

5.1

0.01

220

2.7

1980

0.01

120

2.7

4950

0.0047

5.6

990

0.01

120

5.6

1980

0.0047

5.6

4950

0.0036

Table 7. Suggested Compensation Network for 12V Input

Application Using Multiple Paralleled 330

µF AVX TPS Output

Capacitors

LO (µH)

CO (µF)

RC (kΩ)CC (µF)

C1 (pF)

990

0.82

0.047

1500

1980

1.5

0.033

820

4950

3.9

0.022

330

2.7

990

2.2

0.033

560

2.7

1980

4.3

0.022

270

2.7

4950

0.01

120

5.6

990

4.3

0.022

270

5.6

1980

8.2

0.010

150

5.6

4950

0.010

Tables 6 and 7 show the suggested compensation com-

ponents for 5V and 12V input applications based on the

inductor and output capacitor values. The values were

calculated using multiple paralleled 330

µF AVX TPS series

surface mount tantalum capacitors as the output capaci-

tor. The optimum component values might deviate from

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