9

LTC1235

Voltage Output

During normal operation, the LTC1235 uses a charge

pumped NMOS power switch to achieve low dropout and

low supply current. This power switch can deliver up to

5

0.1

µF or greater to ensure stability. Use of a larger bypass

capacitor is advantageous for supplying current to heavy

transient loads.

When operating currents larger than 50mA are required

ential) is desired, the LTC1235 provides BATT ON output

to drive the base of external PNP transistor (Figure 3).

Another alternative to provide higher current is to connect

pin to supply the extra current.

The LTC1235 is protected for safe area operation with

short circuit limit. Output current is limited to approxi-

mately 200mA. If the device is overloaded for a long period

of time, thermal shutdown turns the power switch off until

the device cools down. The threshold temperature for

thermal shutdown is approximately 155

°C with about

10

°C of hysteresis which prevents the device from oscil-

lating in and out of shutdown.

The PNP switch was not chosen for the internal power

switch because it injects unwanted current into the sub-

petitive devices and adds to the charging current of the

battery which can damage lithium batteries. LTC1235

uses a charge pumped NMOS power switch to eliminate

unwanted charging current while achieving low dropout

and low supply current. Since no current goes to the

junction leakage.

Conditional Battery Backup

battery backup function when primary power is lost.

Disabling the battery backup function is useful in conserv-

ing the backup battery's life when the SRAM doesn't need

battery backup during long term storage of a computer

system, or delivery of the computer system to the end

user.

The BACKUP pin (Pin 8) is used to serve this feature on

threshold, the status of the BACKUP pin (logic low or logic

high) is stored in the Memory Logic (see BLOCK DIA-

comparator, C2, shuts off the NMOS power switch, M1.

M2 is designed for very low dropout voltage (input-to-

output differential). This feature is advantageous for low

current applications such as battery backup in CMOS RAM

and other low power CMOS circuitry. If the stored status

in Battery Saving Mode (see Figure 4). The supply current

in both mode is 1

µA maximum.

is replaced (with power off), the status stored in the

Battery Backup Mode or in Battery Saving Mode. When

C2 has typically 20mV of hysteresis to prevent spurious

status stored in the Memory Logic is high. The response

time of C2 is approximately 20

µs.

Figure 3. Using BATT ON to Drive External PNP Transistor

+5V

+3V

0.1

µF

0.1

µF

LTC1235

GND

ANY PNP POWER TRANSISTOR

LTC1235 F03

BATT ON

R1

S

APPLICATI

I FOR ATIO