6

LTC1235

PI FU CTIO S

with a 0.1

µF capacitor.

Backup: Logic input to control the PMOS switch, M2,

the reset voltage threshold, the status of the BACKUP pin

(logic low or logic high) is latched in Memory Logic and

latched status of the BACKUP pin is high, the Memory

by an internal pullup and the LTC1235 will provide battery

a capacitor of 0.1

µF or greater. During normal operation,

switch, M1, which can deliver up to 50mA and has a typical

on resistance of 5

status of the BACKUP pin stored in Memory Logic controls

M2. If the status is high, the Memory Logic turns on M2

the status of the BACKUP pin stored in the Memory Logic

controls M2. If the status is high, auxiliary power, connected

Saving Mode. If backup battery or auxiliary power is not

GND: Ground pin.

BATT ON: Battery on logic output from comparator C2.

drive for an external PNP transistor to increase the output

PFI: Power Failure Input. PFI is the noninverting input to

the Power Fail Comparator, C3. The inverting input is

internally connected to a 1.3V reference. The Power Failure

Output remains high when PFI is above 1.3V and goes low

C3 is not used.

PFO: Power Failure Output from C3. PFO remains high

when PFI is above 1.3V and goes low when PFI is below

PFO is forced low.

PB RST: Logic input for direct connection to a push-

button. The push-button reset input requires an active low

signal. Internally, this input signal is debounced and timed

for a minimum of 40ms. When this condition is satisfied,

the reset pulse generator forces RESET to active low. The

RESET signal will remain active low for a minimum of

140ms from the moment the push-button reset input is

released from logic low level.

RESET: Logic output for

µP reset control. The LTC1235

provides three ways to generate

µP reset. First, whenever

returns to 5V, the reset pulse generator forces RESET to

remain active low for a minimum of 140ms. Second, when

the watchdog timer is enabled but not serviced prior to the

time-out period, the reset pulse generator also forces

RESET to active low for a minimum of 140ms for every

time-out period (see Figure 11). Third, when the PB RST

pin stays active low for a minimum of 40ms, RESET is

forced low by reset pulse generator. The RESET signal will

remain active low for a minimum of 140ms from the

moment the push-button reset input is released from logic

low level.

RESET: RESET is an active high logic output. It is the

inverse of RESET.

LOW LINE: Logic output from comparator C1. LOW LINE

falls below the reset voltage threshold (4.65V typically),

voltage threshold, LOW LINE returns high (see Figure 1).

Table 1).