8

LTC1664

A3 A2 A1

Address/Control

A0 D9 D8 D7 D6 D5 D4 D3 D2 D1

X1 X0

D0

Input Code

Don’t

Care

Table 1. LTC1664 Input Word

OPERATIO

Transfer Function

The transfer function is

V

k

V

OUT IDEAL

REF









1024

where k is the decimal equivalent of the binary DAC input

Power-On Reset

The LTC1664 clears the outputs to zero scale when power

is first applied, making system initialization consistent and

repeatable.

Power Supply Sequencing

The voltage at REF (Pin 6) should be kept within the range

– 0.2V

Ratings). Particular care should be taken to observe these

limits during power supply turn-on and turn-off sequences,

Serial Interface

input is shifted into the 16-bit shift register on the positive

edge of SCK. The 4-bit DAC address, A3-A0, is loaded first

(see Table 2), then the 10-bit input code, D9-D0, ordered

MSB-to-LSB in each case. Two don’t-care bits, X1-X0, are

loaded last. When the full 16-bit input word has been

shifted in, CS/LD is pulled high, loading the DAC register

with the word and causing the addressed DAC output(s)

to update. The clock is disabled internally when CS/LD is

high. Note: SCK must be low before CS/LD is pulled low.

The buffered serial output of the shift register is available

Multiple LTC1664’s can be controlled from a single 3-wire

“daisy-chain” facility. A series of

m chips is configured by

chip, forming a single 16

m-bit shift register. The SCK and

CS/LD signals are common to all chips in the chain. In use,

CS/LD is held low while

of the first chip; CS/LD is then pulled high, updating all of

them simultaneously.

Sleep Mode

instruction (see Table 2). In this mode, the digital interface

stays active while the analog circuits are disabled; static

power consumption is thus virtually eliminated. The refer-

ence input and analog outputs are set in a high impedance

state and all DAC settings are retained in memory so that

when Sleep mode is exited, the outputs of DACs not

updated by the Wake command are restored to their last

active state.

Sleep mode is initiated by performing a load sequence to

Once in Sleep mode, a load sequence to any other address

causes the LTC1664 to Wake. It is possible to keep one or

more chips of a daisy chain in continuous Sleep mode by

giving the Sleep instruction to these chips each time the

active chips in the chain are updated.