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Fig 1.

Block diagram

001aag268

SAF7115

ANALOG

DUAL

ADC

FRAME LOCKED

AUDIO CLOCK

PLL

PROGRAMMING

REGISTER

ARRAY

BOUNDARY

SCAN

TEST

A/B

REGISTER

MUX

PLL2

AUDIO CLOCK

GENERATION

CGC2

LINE

FIFO

BUFFER

VIDEO

FIFO

VIDEO/TEXT

ARBITER

32

TO

8(16)

MUX

TEXT

FIFO

X PORT I/O FORMATTING

RT OUT

I/O CONTROL

EXPANSION PORT PIN MAPPING

DIGITAL

DECODER

WITH

ADAPTIVE

COMB

FILTER

FIR PREFILTER

PRESCALER

AND

SCALER BCS

VERTICAL

SCALING

HORIZONTAL

FINE

(PHASE)

SCALING

GENERAL

PURPOSE

VBI DATA

SLICER

EVENT CONTROLLER

IPD[7:0]

IDQ

IGPH

IGPV

IGP0

IGP1

ITRDY

ITRI

ICLK

TEST[9:0]

XTRI

XRDY

XRV

AI11

AGND

AI12

AI21

AI22

AI23

AI24

AOUT

AI1D

AI2D

RESO_N

CE

XTOUT

XTALI

XTALO

RTS1

RTS0

RTC0

LLC2

LLC

XPD[7:0]

XRH

XDQ

XCLK

SDA

HPD[7:0]

SCL

TDO

ALRCLK

AMCLK

ASCLK

AXMCLK

TDI

TMS

TCK

TRST_N

PULSE GENERATOR