SAF7115_1

© NXP B.V. 2008. All rights reserved.

Product data sheet

Rev. 01 — 15 October 2008

17 of 35

NXP Semiconductors

SAF7115

Multistandard video decoder

[1]

This setting connects pin AOUT to ground.

[2]

[3]

[4]

The ADC gain difference is

.

[5]

[6]

The levels must be measured with load circuits; 1.2 k

Ω at 3 V (TTL load); C

[7]

illustrated in Figure 3 and Figure 4.

[8]

Valid for outputs: XPD [7:0], XRH, XRV, XDQ, RTS0, RTS1, RTCO

[9]

Valid for inputs: XPD [7:0], HPD [7:0], XRH, XRV, XDQ

[10] Valid for output: XRDY

[11] Valid for outputs: IPD [7:0], HPD [7:0], IGPH, IGPV, IDQ, IGP1, IGP0

[12] Valid for input: ITRDY

rise time

0.6 V to 2.6 V

-

-

5

ns

fall time

2.6 V to 0.6 V

-

-

5

ns

Data and control signal output timing I-port, related to ICLK output (for IPCK[1:0] 87h[5:4] = 11b)

output load capacitance at all outputs

15

-

50

pF

data output hold time

[11] 3-

-

ns

propagation delay

[11] -

-

23

ns

Data and control signal input timing I-port, related to ICLK output (for IPCK[1:0] 87h[5:4] = 11b)

data input set-up time

[12] 18

-

-

ns

data input hold time

[12] --

−2ns

Data and control signal output timing I-port, related to ICLK input (for IPCK[1:0] 87h[5:4] = 11b)

output load capacitance at all outputs

15

-

50

pF

data output hold time

[11] 3-

-

ns

propagation delay

from positive edge of LLC

output

[11] -

-

23

ns

Data and control signal input timing I-port, related to ICLK input (for IPCK[1:0] 87h[5:4] = 01b)

data input set-up time

[12] 12

-

-

ns

data input hold time

[12] --

2

ns

AMCLK clock output

output load capacitance

15

-

50

pF

rise time

0.6 V to 2.6 V

-

-

5

ns

fall time

2.6 V to 0.6 V

-

-

5

ns

Table 7.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

∆G

ADC

maximum deviation

minimum deviation

------------------------------------------------

1

–





100

×

=