ICS831724AKI REVISION A MAY 16, 2013

2

©2013 Integrated Device Technology, Inc

ICS831724I Data Sheet

DIFFERENTIAL CLOCK DATA MULTIPLEXER

Table 1. Pin Descriptions

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Table 2. Pin Characteristics

Number

Name

Type

Description

1, 8, 9, 15,

26, 32

Power

Positive power supply pins.

2

nOED

Input

Pullup

Output enable for the QD output. See Table 3D for function.

LVCMOS/LVTTL interface levels.

3

CLK0

Input

Pulldown

Non-inverting clock/data input 0.

4

nCLK0

Input

Pulldown/Pullup

5

CLK1

Input

Pulldown

Non-inverting clock/data input 1.

6

nCLK1

Input

Pulldown/Pullup

7

nOEA

Input

Pullup

Output enable for the QA output. See Table 3A for function.

LVCMOS/LVTTL interface levels.

10, 11

QA, nQA

Output

Differential output pair A. HCSL interface levels.

12, 29

GND

Power

Power supply ground.

13, 14

QB, nQB

Output

Differential output pair B. HCSL interface levels.

16

nOEB

Input

Pullup

Output enable for the QB output. See Table 3B for function.

LVCMOS/LVTTL interface levels.

17, 19, 20,

21, 22, 24

nc

Unused

No connect pins.

18

SEL

Input

Pulldown

Input select. See Table 3E for function.

LVCMOS/LVTTL interface levels.

23

nOEC

Input

Pullup

Output enable for the QC output. See Table 3C for function.

LVCMOS/LVTTL interface levels.

25

IREF

Input

An external fixed precision resistor (475

provides a reference current used for the differential current-mode QX,

nQX outputs.

27, 28

QC, nQC

Output

Differential output pair C. HCSL interface levels.

30, 31

QD, nQD

Output

Differential output pair D. HCSL interface levels.

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

Input Capacitance

4

pF

Input Pullup Resistor

51

k



51

k

