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IRMCK341 数据表(PDF) 33 Page - International Rectifier |
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IRMCK341 数据表(HTML) 33 Page - International Rectifier |
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33 / 36 page ![]() IRMCK341 www.irf.com © 2007 International Rectifier 33 Pin Number Pin Name Internal Pull-up /Pull-down Pin Type Description 33 AIN2 I Analog input channel 2, 0-1.2V range, needs to be pulled down to AVSS if unused 34 AIN3 I Analog input channel 3, 0-1.2V range, needs to be pulled down to AVSS if unused 35 AIN4 I Analog input channel 4, 0-1.2V range, needs to be pulled down to AVSS if unused 36 AIN5 I Analog input channel 5, 0-1.2V range, needs to be pulled down to AVSS if unused 37 AIN6 I Analog input channel 6, 0-1.2V range, needs to be pulled down to AVSS if unused 38 VDD2 P 1.8V digital power 39 VSS P Digital common 40 VDD1 P 3.3V digital power 41 GATEKILL I PWM shutdown input, 2-μsec digital filter, configurable either high or low true. 42 PWMWL 70 kΩ Pull up O PWM gate drive for phase W low side, configurable either high or low true 43 PWMWH 70 kΩ Pull up O PWM gate drive for phase W high side, configurable either high or low true 44 PWMVL 70 kΩ Pull up O PWM gate drive for phase V low side, configurable either high or low true 45 PWMVH 70 kΩ Pull up O PWM gate drive for phase V high side, configurable either high or low true 46 PWMUL 70 kΩ Pull up O PWM gate drive for phase U low side, configurable either high or low true 47 PWMUH 70 kΩ Pull up O PWM gate drive for phase U high side, configurable either high or low true 48 P3.0/INT2/CS1 I/O Discrete programmable I/O or external interrupt 2 input or SPI Chip Select 1 49 P3.1/AOPWM2 I/O Discrete programmable I/O or PWM 2 digital output 50 P3.2/INT0 I/O Discrete programmable I/O or Interrupt 0 input 51 P3.3/INT1 I/O Discrete programmable I/O or Interrupt 1 input 52 P3.5/T1 I/O Discrete programmable I/O or Timer/Counter 1 53 VSS P Digital common 54 VDD1 P 3.3V digital power 55 SCL/SO- SI/VPP I/O I2C clock output (open drain, need pull up) or SPI data or OTP power supply for programming 56 SDA/CS0 I/O I2C data (open drain, need pull up) or SPI Chip Select 0 57 P5.1/TMS I/O JTAG test mode select 58 P5.2/TDO I/O JTAG test data output 59 P5.3/TDI I/O JTAG test data input 60 TCK I JTAG test clock |
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