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M35046-059FP 数据表(PDF) 13 Page - Mitsubishi Electric Semiconductor

部件名 M35046-059FP
功能描述  SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
PDF  40 Pages
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制造商  MITSUBISHI [Mitsubishi Electric Semiconductor]
网页  http://www.mitsubishichips.com
标志 MITSUBISHI - Mitsubishi Electric Semiconductor

M35046-059FP 数据表(HTML) 13 Page - Mitsubishi Electric Semiconductor

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MITSUBISHI MICROCOMPUTERS
M35046-XXXSP/FP
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
13
Sets all raster blanking
Synchronize with the front porch or
back porch of the horizontal
synchronazation signal.
This register has or do not have mask
at phase comparison operating.
Set VERT pin polarity.
Set HOR pin polarity.
Set blanking mode. (Note 1)
An example of blanking mode at
BCOL = “0”, DSPn = “0” (n = 0 to 11)
shown left.
(Note 2)
There is no need to reset because
there is no register for this bit.
R, G, B and BLNK0 output can be
altered.
Display can be altered.
Blinking duty ratio can be altered.
Blinking frequency can be altered.
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
(9) Address 12816
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
BCOL
__
B/F
VMASK
POLV
POLH
BLK0
BLK1
SYAD
RAMERS
STOP
DSPON
BLINK0
BLINK1
BLINK2
TEST13
Register
DA
Status
Contents
Function
Remarks
BLINK
1
0
0
1
1
0
0
1
0
1
Duty
Blinking OFF
25%
50%
75%
1
0
0
1
1
0
0
1
0
1
Blanking mode
Matrix-outline size
Character size
Border size
Matrix-outline size
BLK
Notes 1: Refer to DISPLAY FORM 1
2: Refer to DISPLAY FORM 3
Blanking of BLK0, BLK1
All raster blanking
Synchronize with the leading edge of horizontal synchronization.
Synchronize with the trailing edge of horizontal synchronization.
Do not mask by VERT input signal
Mask by VERT input signal
VERT pin is negative polarity
VERT pin is positive polarity
HOR pin is negative polarity
HOR pin is positive polarity
Border display of character
Shadow display of character
RAM not erased
RAM erased
Oscillation of clock for display
Stop the oscillation of clock for display
Display OFF
Display ON
Divided into 64 of vertical synchronous signal
Divided into 32 of vertical synchronous signal
It should be fixed to “0”.
Test mode



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