Interface Kit for EV9900A

EV9902

Figure 6 – The PLL Registers Tab

To calculate the value of the Clock Control register to generate a desired bit rate:

1.

Enter the reference clock frequency, in MHz, which for the default configuration of the

EV9900A is 14.4MHz

2.

Enter the desired bit rate, in bps

3.

Click the ‘Calculate Reg Value’ button

The value displayed for Clock Control register will then be updated to that required to generate

the desired bit rate. A pop-up window will appear, if the desired bit rate can not be generated by

the CMX990 with the current reference clock frequency. It may be possible to achieve the

desired bit rate by adjusting the reference clock frequency, see the CMX990 and EV9900A

datasheets for more information.

6.1.5.

The Modem Transfers Tab

The Modem Transfers tab allows the EV9900A to transmit or receive single frames over a RF link,

see Figure 7. Two different types of frames can be transferred:

•

Mobitex Frames consisting of a Mobitex frame header followed by 0-32 Mobitex 240 bit

data block(s)

•

Unformatted data frames consisting of a small header (16 bits of bit synchronisation and

16 bits of frame synchronisation) followed by 0-255 byte(s).

©

CML Microsystems Plc

13

2009

UM9902/3