PUSB3AB4

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© NXP Semiconductors N.V. 2015. All rights reserved.

Objective data sheet

Rev. 1 — 25 August 2015

3 of 9

NXP Semiconductors

PUSB3AB4

ESD protection for ultra high-speed interfaces

6.

Characteristics

[1]

This parameter is guaranteed by design.

[2]

100 ns Transmission Line Pulse (TLP); 50

; pulser at 80 ns.

[3]

According to IEC 61000-4-5 (8/20

s current waveform).

The device uses an advanced clamping structure showing a negative dynamic resistance.

This snapback behavior strongly reduces the clamping voltage to the system behind the

ESD protection during an ESD event. Do not connect unlimited DC current sources to the

data lines to avoid keeping the ESD protection device in snap-back state after exceeding

breakdown voltage (due to an ESD pulse for instance).

7.

Application information

The device is designed to provide high-level ESD protection for high-speed serial

data buses such as HDMI, DisplayPort, eSATA and LVDS data lines.

When designing the PCB, give careful consideration to impedance matching and signal

coupling. Do not connect the signal lines to unlimited current sources like, for example, a

battery.

Table 5.

Characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

breakdown voltage

5.5

9

-

V

-

<1

100

nA

forward voltage

-0.7

-V

line capacitance

[1] -

0.17

0.2

pF

dynamic resistance

TLP

[2]

positive transient

-

0.4

-



negative transient

-

0.4

-



snapback voltage

-

3.3

-

V

clamping voltage

[3] -4.5

-V

negative transient

[3] -

4.5

-

V