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AM4376 数据表(PDF) 31 Page - Texas Instruments

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部件名 AM4376
功能描述  AM437x Sitara??Processors
PDF  261 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

AM4376 数据表(HTML) 31 Page - Texas Instruments

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AM4376, AM4377, AM4378, AM4379
www.ti.com
SPRS851B – JUNE 2014 – REVISED APRIL 2015
Table 4-10. Pin Attributes (ZDN Package) (continued)
BALL
BALL
BALL RESET
BUFFER
PULL
BALL
RESET
PIN NAME [2]
SIGNAL NAME [3]
MODE [4]
TYPE [5]
RESET
REL. MODE
POWER [9]
HYS [10]
STRENGTH
UP/DOWN
IO CELL [13]
NUMBER [1]
REL.
STATE [6]
[8]
(mA) [11]
TYPE [12]
STATE [7]
V1
ddr_d20
ddr_d20
0x0
IO
PD
Mode0
VDDS_DDR
YES
8
PU/PD
LVCMOS/HST
L/HSUL_12
W4
ddr_d21
ddr_d21
0x0
IO
PD
Mode0
VDDS_DDR
YES
8
PU/PD
LVCMOS/HST
L/HSUL_12
W5
ddr_d22
ddr_d22
0x0
IO
PD
Mode0
VDDS_DDR
YES
8
PU/PD
LVCMOS/HST
L/HSUL_12
W6
ddr_d23
ddr_d23
0x0
IO
PD
Mode0
VDDS_DDR
YES
8
PU/PD
LVCMOS/HST
L/HSUL_12
Y2
ddr_d24
ddr_d24
0x0
IO
PD
Mode0
VDDS_DDR
YES
8
PU/PD
LVCMOS/HST
L/HSUL_12
Y3
ddr_d25
ddr_d25
0x0
IO
PD
Mode0
VDDS_DDR
YES
8
PU/PD
LVCMOS/HST
L/HSUL_12
Y4
ddr_d26
ddr_d26
0x0
IO
PD
Mode0
VDDS_DDR
YES
8
PU/PD
LVCMOS/HST
L/HSUL_12
AA3
ddr_d27
ddr_d27
0x0
IO
PD
Mode0
VDDS_DDR
YES
8
PU/PD
LVCMOS/HST
L/HSUL_12
AB2
ddr_d28
ddr_d28
0x0
IO
PD
Mode0
VDDS_DDR
YES
8
PU/PD
LVCMOS/HST
L/HSUL_12
AB1
ddr_d29
ddr_d29
0x0
IO
PD
Mode0
VDDS_DDR
YES
8
PU/PD
LVCMOS/HST
L/HSUL_12
AC1
ddr_d30
ddr_d30
0x0
IO
PD
Mode0
VDDS_DDR
YES
8
PU/PD
LVCMOS/HST
L/HSUL_12
AC2
ddr_d31
ddr_d31
0x0
IO
PD
Mode0
VDDS_DDR
YES
8
PU/PD
LVCMOS/HST
L/HSUL_12
F4
ddr_dqm0
ddr_dqm0
0x0
O
PU
Mode0
VDDS_DDR
YES
8
PU/PD
LVCMOS/HST
L/HSUL_12
H2
ddr_dqm1
ddr_dqm1
0x0
O
PU
Mode0
VDDS_DDR
YES
8
PU/PD
LVCMOS/HST
L/HSUL_12
V6
ddr_dqm2
ddr_dqm2
0x0
O
PU
Mode0
VDDS_DDR
YES
8
PU/PD
LVCMOS/HST
L/HSUL_12
Y1
ddr_dqm3
ddr_dqm3
0x0
O
PU
Mode0
VDDS_DDR
YES
8
PU/PD
LVCMOS/HST
L/HSUL_12
F2
ddr_dqs0
ddr_dqs0
0x0
IO
PD
Mode0
VDDS_DDR
YES
8
PU/PD
LVCMOS/HST
L/HSUL_12
J2
ddr_dqs1
ddr_dqs1
0x0
IO
PD
Mode0
VDDS_DDR
YES
8
PU/PD
LVCMOS/HST
L/HSUL_12
W1
ddr_dqs2
ddr_dqs2
0x0
IO
PD
Mode0
VDDS_DDR
YES
8
PU/PD
LVCMOS/HST
L/HSUL_12
AA1
ddr_dqs3
ddr_dqs3
0x0
IO
PD
Mode0
VDDS_DDR
YES
8
PU/PD
LVCMOS/HST
L/HSUL_12
F1
ddr_dqsn0
ddr_dqsn0
0x0
IO
PU
Mode0
VDDS_DDR
Yes
8
PU/PD
LVCMOS/HST
L/HSUL_12
J1
ddr_dqsn1
ddr_dqsn1
0x0
IO
PU
Mode0
VDDS_DDR
Yes
8
PU/PD
LVCMOS/HST
L/HSUL_12
W2
ddr_dqsn2
ddr_dqsn2
0x0
IO
PU
Mode0
VDDS_DDR
Yes
8
PU/PD
LVCMOS/HST
L/HSUL_12
Copyright © 2014–2015, Texas Instruments Incorporated
Terminal Configuration and Functions
31
Submit Documentation Feedback
Product Folder Links: AM4376 AM4377 AM4378 AM4379



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