TLS710B0

General Product Characteristics

Data Sheet

6

Rev. 1.0, 2015-03-12

4.2

Functional Range

Note: Within the functional range the IC operates as described in the circuit description. The electrical

characteristics are specified within the conditions given in the related electrical characteristics table.

4.3

Thermal Resistance

Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go

to www.jedec.org.

Table 2

Functional Range

Parameter

Symbol

Values

Unit

Note /

Test Condition

Number

Min.

Typ.

Max.

Input Voltage Range for Normal

Operation

V

I

V

40

V

–

P_4.2.1

Extended Input Voltage Range

V

I,ext

4.0

–

40

V

–

1)

1) When

V

P_4.2.2

Enable Voltage Range

V

EN

0

–

40

V

–

P_4.2.3

Output Capacitor’s Requirements

for Stability

C

Q

1–

–

µF

2) The minimum output capacitance requirement is applicable for a worst case capacitance tolerance of 30%

P_4.2.4

Output Capacitor’s ESR

ESR(C

–

5

Ω

3) Relevant ESR value at

P_4.2.5

Junction Temperature

T

i

-40

–

150

°C

–

P_4.2.6

Table 3

Thermal Resistance

Parameter

Symbol

Values

Unit

Note / Test Condition

Number

Min.

Typ.

Max.

Package Version PG-DSO-8 EP

1) Not subject to production test, specified by design

R

thJC

–

13

–

K/W

–

P_4.3.1

Junction to Ambient

R

thJA

–

46

–

K/W

2) Specified

R

(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm³ board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu).

Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.

P_4.3.2

Junction to Ambient

R

thJA

–

153

–

K/W

1s0p board, footprint

3) Specified

R

P_4.3.3

Junction to Ambient

R

thJA

–

71

–

K/W

heatsink area on PCB3)

P_4.3.4

Junction to Ambient

R

thJA

–

59

–

K/W

heatsink area on PCB3)

P_4.3.5