ZL6105ALAF datasheet(22/35 Pages) INTERSIL

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ZL6105

FN6906.5

December 19, 2013

Non-linear Response (NLR) Settings

The ZL6105 incorporates a non-linear response (NLR) loop that

decreases the response time and the output voltage deviation in

the event of a sudden output load current step. The NLR loop

incorporates a secondary error signal processing path that

bypasses the primary error loop when the output begins to

transition outside of the standard regulation limits. This scheme

results in a higher equivalent loop bandwidth than what is

possible using a traditional linear loop.

When a load current step function imposed on the output causes

the output voltage to drop below the lower regulation limit, the

NLR circuitry will force a positive correction signal that will turn

on the upper MOSFET and quickly force the output to increase.

Conversely, a negative load step (i.e. removing a large load

current) will cause the NLR circuitry to force a negative correction

signal that will turn on the lower MOSFET and quickly force the

output to decrease.

NLR can be configured using resistor pin-straps as follows:

• CFG0 disables NLR or enables NLR inner thresholds to 1.5%,

2% or 3% (see Table 29).

• CFG1 sets NLR inner thresholds timeout and blanking to 1 and

4 or 2 and 8 (see Table 26).

Please refer to Application Note AN2032 for more details

regarding NLR settings.

Efficiency Optimized Driver Dead-time

Control

The ZL6105 utilizes a closed loop algorithm to optimize the

dead-time applied between the gate drive signals for the top and

bottom FETs. In a synchronous buck converter, the MOSFET drive

circuitry must be designed such that the top and bottom

MOSFETs are never in the conducting state at the same time.

Potentially damaging currents flow in the circuit if both top and

bottom MOSFETs are simultaneously on for periods of time

exceeding a few nanoseconds. Conversely, long periods of time in

which both MOSFETs are off reduce overall circuit efficiency by

allowing current to flow in their parasitic body diodes.

It is therefore advantageous to minimize this dead-time to

provide optimum circuit efficiency. In the first order model of a

buck converter, the duty cycle is determined by Equation 32:

However, non-idealities exist that cause the real duty cycle to

extend beyond the ideal. Dead-time is one of those non-idealities

that can be manipulated to improve efficiency. The ZL6105 has

an internal algorithm that constantly adjusts dead-time

non-overlap to minimize duty cycle, thus maximizing efficiency.

This circuit will null out dead-time differences due to component

variation, temperature, and loading effects.

This algorithm is independent of application circuit parameters such

as MOSFET type, gate driver delays, rise and fall times and circuit

layout. In addition, it does not require drive or MOSFET voltage or

current waveform measurements.

Adaptive Diode Emulation

Most power converters use synchronous rectification to optimize

efficiency over a wide range of input and output conditions.

However, at light loads the synchronous MOSFET will typically

sink current and introduce additional energy losses associated

with higher peak inductor currents, resulting in reduced

efficiency. Adaptive diode emulation mode turns off the low-side

FET gate drive at low load currents to prevent the inductor current

from going negative, reducing the energy losses and increasing

overall efficiency.

Note: the overall bandwidth of the device may be reduced when

in diode emulation mode. It is recommended that diode

emulation is disabled prior to applying significant load steps.

Power Management Functional

Description

Input Undervoltage Lockout

The input undervoltage lockout (UVLO) prevents the ZL6105 from

operating when the input falls below a preset threshold,

indicating the input supply is out of its specified range. The UVLO

threshold (VUVLO) can be set between 2.85V and 16V using the

UVLO pin. The simplest implementation is to connect the UVLO

pin as shown in Table 18. If the UVLO pin is left unconnected, the

UVLO threshold will default to 4.5V.

TABLE 17. FC1 PIN-STRAP SETTINGS

FC1 PIN

AUTO COMP GAIN

LOW

100%

OPEN

50%

HIGH

30%

10kΩ

10%

11kΩ

20%

12.1kΩ

30%

13.3kΩ

40%

14.7kΩ

50%

16.2kΩ

60%

17.8kΩ

70%

19.6kΩ

80%

21.5kΩ

90%

23.7kΩ

100%

TABLE 18. UVLO THRESHOLD PIN-STRAP SETTINGS

UVLO PIN

UVLO THRESHOLD (V)

LOW

OPEN

4.5

HIGH

10.8

OUT

≈

(EQ. 32)

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