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DS11181D-page 6

Preliminary

© 1996 Microchip Technology Inc.

FIGURE 2-1:

SYNCHRONOUS DATA TIMING

FIGURE 2-2:

READ TIMING

FIGURE 2-3:

EWEN TIMING

CLK

STATUS VALID

CS

DI

DO

(READ)

DO

(PROGRAM)

PRE

PE

CLK

CS

A2

• • •

A0

0

1

1

DI

DO

* The memory automatically cycles to the next register.

Tri-State is a registered trademark of National Semiconductor.

D15

• • •

D0

0

D15*

• • •

D0

D15*

PRE = 0

PE = X

• • •

CLK

CS

0

0

1

DI

1

1

• • •

XX

PRE = 0

DO = TRI-STATE

PE

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