© 1996 Microchip Technology Inc.

Preliminary

DS11181D-page 9

93LCS56/66

FIGURE 2-10: PREN TIMING

FIGURE 2-11: PRCLEAR TIMING

FIGURE 2-12: PRWRITE TIMING

CLK

CS

1

DI

X

• • •

01

PE

X

DO = TRI-STATE

A EWEN cycle must precede a PREN cycle.

PRE

0

1

6 DON'T CARE BITS

CLK

CS

1

DI

BUSY

• • •

READY

DO

1

TRI-STATE

PE

PRE

1

11

11

1

A PREN cycle must immediately precede a PRCLEAR cycle.

8 BITS OF "1"

CLK

CS

0

DI

BUSY

READY

DO

1

PE

PRE

1

A7

• • •

A0

Protect Register MUST be cleared before a PRWRITE cycle.

A PREN cycle must immediately precede a PRWRITE cycle.

Address bit A7 is a "don't care" for 93LCS56.