HCS512

© 1997 Microchip Technology Inc.

DS40151C-page 5

3.0

DESCRIPTION OF FUNCTIONS

3.1

Parallel Interface

The HCS512 activates the S3, S2, S1 & S0 outputs

according to Table 3-1 when a new valid code is

received. The outputs will be activated for approxi-

mately 500 ms. If a repeated code is received during

this time, the output extends for approximately 500 ms.

TABLE 3-1:

FUNCTION OUTPUT TABLE

3.2

Serial Interface

The decoder has a PWM/Synchronous interface con-

nection to microcontrollers with limited I/O. An output

data stream is generated when a valid transmission is

received. The data stream consists of one start bit, four

function bits, one bit for battery status, one bit to indi-

cate a repeated transmission, two status bits, and one

stop bit. (Table 3-1). The DATA and CLK lines are used

to send a synchronous event message.

A special status message is transmitted on the second

pass of learn. This allows the controlling microcontroller

to determine if the learn was successful (Result = 1)

and if a previous transmitter was overwritten (Overwrite

= 1). The status message is shown in Figure 3-2.

Table 3-2 show the values for TX1:0 and the number of

transmitters learned.

TABLE 3-2:

STATUS BITS

FIGURE 3-1:

DATA OUTPUT FORMAT

FIGURE 3-2:

STATUS MESSAGE FORMAT

A 1-wire PWM or 2-wire synchronous interface can be used.

In 1-wire mode, the data is transmitted as a PWM signal with a basic pulse width of 400

µs.

In 2-wire mode, synchronous mode PWM bits start on the rising edge of the clock, and the bits must be sampled on the

falling edge. The start and stop bits are ‘1’.

FIGURE 3-3:

PWM TRANSMISSION FORMAT

Function

Code

S3

S2

S1

S0

0001

0

0

0

1

0010

0

0

1

0

0011

0

0

1

1

0100

0

1

0

0

0101

0

1

0

1

0110

0

1

1

0

0111

0

1

1

1

1000

1

0

0

0

1001

1

0

0

1

1010

1

0

1

0

1011

1

0

1

1

1100

1

1

0

0

1101

1

1

0

1

1110

1

1

1

0

1111

1

1

1

1

TX1

TX0

Number of Transmitters

0

0

One

0

1

Two

1

0

Three

1

1

Four

START

S3

S2

S1

S0

TX1

TX0

STOP

REPEAT

START

0

0

0

0

RESULT

TX1

TX0

STOP

OVRWR

S3

Start

S2

S1

S0

RPT Reserved Reserved Stop

1200

µs

CLK

DATA

“1”

“0”

600

µs