PIC16F877-04SLASHP datasheet(76/218 Pages) MICROCHIP

76 / 218 page

PIC16F87X

DS30292C-page 74

 2001 Microchip Technology Inc.

9.2.1

SLAVE MODE

In Slave mode, the SCL and SDA pins must be config-

ured as inputs. The MSSP module will override the

input state with the output data, when required (slave-

transmitter).

When an address is matched, or the data transfer after

an address match is received, the hardware automati-

cally will generate the Acknowledge (ACK) pulse, and

then load the SSPBUF register with the received value

currently in the SSPSR register.

There are certain conditions that will cause the MSSP

module not to give this ACK pulse. These are if either

(or both):

The buffer full bit BF (SSPSTAT<0>) was set

before the transfer was received.

The overflow bit SSPOV (SSPCON<6>) was set

before the transfer was received.

If the BF bit is set, the SSPSR register value is not

loaded into the SSPBUF, but bit SSPIF and SSPOV are

set. Table 9-2 shows what happens when a data trans-

fer byte is received, given the status of bits BF and

SSPOV. The shaded cells show the condition where

user software did not properly clear the overflow condi-

tion. Flag bit BF is cleared by reading the SSPBUF reg-

ister, while bit SSPOV is cleared through software.

The SCL clock input must have a minimum high and

low time for proper operation. The high and low times

of the I2C specification, as well as the requirement of

the MSSP module, is shown in timing parameter #100

and parameter #101 of the electrical specifications.

9.2.1.1

Addressing

Once the MSSP module has been enabled, it waits for

a START condition to occur. Following the START con-

dition, the 8-bits are shifted into the SSPSR register. All

incoming bits are sampled with the rising edge of the

clock (SCL) line. The value of register SSPSR<7:1> is

compared to the value of the SSPADD register. The

address is compared on the falling edge of the eighth

clock (SCL) pulse. If the addresses match, and the BF

and SSPOV bits are clear, the following events occur:

The SSPSR register value is loaded into the

SSPBUF register on the falling edge of the 8th

SCL pulse.

The buffer full bit, BF, is set on the falling edge

of the 8th SCL pulse.

An ACK pulse is generated.

SSP interrupt flag bit, SSPIF (PIR1<3>), is set

(interrupt is generated if enabled) on the falling

edge of the 9th SCL pulse.

In 10-bit address mode, two address bytes need to be

received by the slave. The five Most Significant bits

(MSbs) of the first address byte specify if this is a 10-bit

address. Bit R/W (SSPSTAT<2>) must specify a write so

the slave device will receive the second address byte.

For a 10-bit address, the first byte would equal

‘1111 0 A9 A8 0’, where A9 and A8 are the two MSbs

of the address. The sequence of events for a 10-bit

address is as follows, with steps 7-9 for slave-transmitter:

Receive first (high) byte of Address (bits SSPIF,

BF and UA (SSPSTAT<1>) are set).

Update the SSPADD register with the second

(low) byte of Address (clears bit UA and

releases the SCL line).

Read the SSPBUF register (clears bit BF) and

clear flag bit SSPIF.

Receive second (low) byte of Address (bits

SSPIF, BF and UA are set).

Update the SSPADD register with the first (high)

byte of Address. This will clear bit UA and

release the SCL line.

Read the SSPBUF register (clears bit BF) and

clear flag bit SSPIF.

Receive Repeated Start condition.

Receive first (high) byte of Address (bits SSPIF

and BF are set).

Read the SSPBUF register (clears bit BF) and

clear flag bit SSPIF.

9.2.1.2

Slave Reception

When the R/W bit of the address byte is clear and an

address match occurs, the R/W bit of the SSPSTAT

the SSPBUF register.

When the address byte overflow condition exists, then

no Acknowledge (ACK) pulse is given. An overflow

condition is defined as either bit BF (SSPSTAT<0>) is

set, or bit SSPOV (SSPCON<6>) is set. This is an error

condition due to user firmware.

An SSP interrupt is generated for each data transfer

byte. Flag bit SSPIF (PIR1<3>) must be cleared in soft-

ware. The SSPSTAT register is used to determine the

status of the received byte.

Note:

Following the Repeated START condition

(step 7) in 10-bit mode, the user only

needs to match the first 7-bit address. The

user does not update the SSPADD for the

second half of the address.

Note:

The SSPBUF will be loaded if the SSPOV

bit is set and the BF flag is cleared. If a

read of the SSPBUF was performed, but

the user did not clear the state of the

SSPOV

bit

before

the

receive

occurred, the ACK is not sent and the

SSPBUF is updated.

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