PIC16F877-04SLASHP datasheet(77/218 Pages) MICROCHIP

77 / 218 page

 2001 Microchip Technology Inc.

DS30292C-page 75

PIC16F87X

TABLE 9-2:

DATA TRANSFER RECEIVED BYTE ACTIONS

9.2.1.3

Slave Transmission

When the R/W bit of the incoming address byte is set

and an address match occurs, the R/W bit of the

SSPSTAT register is set. The received address is

loaded into the SSPBUF register. The ACK pulse will

be sent on the ninth bit, and the SCL pin is held low.

The transmit data must be loaded into the SSPBUF

the SCL pin should be enabled by setting bit CKP

(SSPCON<4>). The master must monitor the SCL pin

prior to asserting another clock pulse. The slave

devices may be holding off the master by stretching the

clock. The eight data bits are shifted out on the falling

edge of the SCL input. This ensures that the SDA sig-

nal is valid during the SCL high time (Figure 9-7).

An SSP interrupt is generated for each data transfer

byte. The SSPIF flag bit must be cleared in software

and the SSPSTAT register is used to determine the sta-

tus of the byte transfer. The SSPIF flag bit is set on the

falling edge of the ninth clock pulse.

As a slave-transmitter, the ACK pulse from the master

receiver is latched on the rising edge of the ninth SCL

input pulse. If the SDA line is high (not ACK), then the

data transfer is complete. When the not ACK is latched

by the slave, the slave logic is reset and the slave then

monitors for another occurrence of the START bit. If the

SDA line was low (ACK), the transmit data must be

loaded into the SSPBUF register, which also loads the

SSPSR register. Then the SCL pin should be enabled

by setting the CKP bit.

FIGURE 9-6:

I2C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)

Status Bits as Data

Transfer is Received

SSPSR

→ SSPBUF

Generate ACK

Pulse

Set bit SSPIF

(SSP Interrupt occurs

if enabled)

SSPOV

Yes

Note:

Shaded cells show the conditions where the user software did not properly clear the overflow condition.

A7 A6 A5 A4 A3 A2 A1

SDA

SCL

Bus Master

Terminates

Transfer

Bit SSPOV is set because the SSPBUF register is still full.

Cleared in software

SSPBUF register is read

ACK

Receiving Data

ACK

R/W=0

Receiving Address

SSPIF

BF (SSPSTAT<0>)

SSPOV (SSPCON<6>)

ACK

ACK is not sent.

Not

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