TC534CPL datasheet(10/22 Pages) MICROCHIP

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TC530/TC534

DS21433B-page 10

3.4

Reference De-integrate Phase

(DINT)

This phase consists of measuring the time for the inte-

grator output to return (at a rate determined by the

external reference voltage) from its initial voltage to 0V.

The resulting timer data is stored in the output shift reg-

ister as converted analog data.

3.5

Integrator Output Zero Phase (IZ)

This phase ensures the integrator output is at zero volts

when the AZ phase is entered so that only true system

offset voltages will be compensated for.

All internal converter timing is derived from the fre-

quency source at OSCIN and OSCOUT. This frequency

source must be either an externally provided clock

signal or an external crystal. If an external clock is

used, it must be connected to the OSCIN pin and the

OSCOUT pin must remain floating. If a crystal is used, it

must be connected between OSCIN and OSCOUT and

be physically located as close to the OSCIN and

OSCOUT pins as possible. In either case, the incoming

clock frequency is divided by four, with the resulting

clock serving as the internal TC530/TC534 timebase.

4.0

TYPICAL APPLICATIONS

4.1

Programming the TC530/TC534

4.1.1

AZ AND INT PHASE DURATION

These two phases have equal duration determined by

the crystal (or external) frequency and the timer initial-

ization byte (LOAD VALUE). Timing is selected as

follows:

Select Integration Time

Integrationtimemust bepickedasamultiple of the

period of the line frequency. For example, TINT

times of 33msec, 66msec and 132msec maximize

60Hz line rejection.

Estimate Crystal Frequency

Crystal frequencies as high as 2MHz are allowed.

Crystal frequency is estimated using:

EQUATION 4-1:

Calculate LOAD VALUE

EQUATION 4-2:

FIN can be adjusted to a standard value during this

step. The resulting base, -10 LOAD VALUE, must be

converted to a hexadecimal number and then loaded

into the serial port prior to initiating A/D conversion.

4.2

DINT and IZ Phase Timing

The duration of the DINT phase is a function of the

amount of voltage stored on the integrator capacitor

during INT and the value of VREF. The DINT phase is ini-

tiated immediately following INT and terminated when

an integrator output zero crossing is detected. In gen-

eral, the maximum number of counts chosen for DINT is

twice thatofINT (with VREF chosen at VIN(MAX)/2).

4.3

System RESET

The TC530/TC534 must be forced into the AZ state

when power is first applied. A .01

µF capacitor con-

nected from RESET to VDD (or external system reset

logic signal) can be used to momentarily drive RESET

high for a minimum of 100msec.

4.4

Design Example

Figure 4-1 shows a typical TC534 interrupt-driven

application. Timing and component values are calcu-

lated from equations and recommendations made in

Section 3.1 and Section 4.1 of this document. The

EOC connection to the processor INT input is for inter-

rupt-driven applications only. (In polled systems, the

EOC output is available on DOUT).

Given:

Required resolution:16-bits (65,536 counts.)

Maximum: VIN ±2V

Power supply voltage: +5V

60hz system

Pick Integration time (TINT): 66msec

Estimate crystal frequency.

EXAMPLE 4-1:

Calculate LOAD VALUE

EXAMPLE 4-2:

2(R)/TINT

where:

= Desired Converter Resolution (in counts)

FIN = Input Frequency (in MHz)

INT = Integration Time (in seconds)

256 - (TINT)(FIN)

[LOAD VALUE]10 =

1024

FIN =2R/TINT = 2 x 65536/66 x 10

-3 =1.98MHz

(use 2MHz)

LOAD VALUE = 256 – (TINT)(FIN)/1024 = [128]10

[128]10 = 80 hex

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