TC850CPL datasheet(6/26 Pages) MICROCHIP

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TC850

DS21479C-page 6

2.0

PIN DESCRIPTIONS

The descriptions of the pins are listed in Table .

TABLE 2-1:

PIN FUNCTION TABLE

Pin Number

(40-Pin

PDIP/CERDIP)

Pin Number

(44-Pin PLCC)

Symbol

Description

Chip Select, active HIGH. Logically ANDed, with CE to enable read and write

inputs (Note 1).

Chip enable, active LOW (Note 2).

Write input, active LOW. When chip is selected (CS = HIGH and CE = LOW) and

in Demand mode (CONT/DEMAND = LOW), a logic LOW on WR starts a

conversion (Note 1).

Read input, active LOW. When CS = HIGH and CE = LOW, a logic LOW on RD

enables the 3-state data outputs (Note 2).

CONT/

DEMAND

Conversion control input. When CONT/DEMAND = LOW, conversions are initi-

ated by the WR input. When CONT/DEMAND = HIGH, conversions are

performed continuously (Note 1).

OVR/POL

Overrange/polarity data-select input. When making conversions in the Demand

mode (CONT/DEMAND = LOW), OVR/POL controls the data output on DB7

when the high-order byte is active (Note 2).

L/H

Low/high byte-select input. When CONT/DEMAND = LOW, this input controls

whether low-byte or high-byte data is enabled on DB0 through DB7 (Note 2).

DB7

Most Significant data bit output. When reading the A/D conversion result, the

polarity, overrange and DB7 data are output on this pin.

9-15

10-17

DB6-DB0

Data outputs DB6-DB0. 3-state, bus compatible.

BUSY

A/D conversion status output. BUSY goes to a logic HIGH at the beginning of the

de-integrate phase, then goes LOW when conversion is complete. The falling

edge of BUSY can be used to generate a

μP interrupt.

OSC1

Crystal oscillator connection or external oscillator input.

OSC2

Crystal oscillator connection.

TEST

For factory testing purposes only. Do not make external connection to this pin.

DGND

Digital ground connection.

COMP

Connection for comparator auto-zero capacitor. Bypass to VSS with 0.1 μF.

VSS

Negative power supply connection, typically -5V.

INTOUT

Output of the integrator amplifier. Connect to CINT.

INTIN

Input to the integrator amplifier. Connect to summing node of RINT and CINT.

BUFFER

Output of the input buffer. Connect to RINT.

CBUFB

Connection for buffer auto-zero capacitor. Bypass to VSS with 0.1 μF.

CBUFA

Connection to buffer auto-zero capacitor. Bypass to VSS with 0.1 μF.

CINTA

Connection for integrator auto-zero capacitor. Bypass to VSS with 0.1 μF.

CINTB

Connection for integrator auto-zero capacitor. Bypass to VSS with 0.1 μF.

ANALOG

COMMON

Analog common.

IN–

Negative differential analog input.

IN+

Positive differential analog input.

Note

This pin incorporates a pull-down resistor to DGND.

2: This pin incorporates a pull-up resistor to VDD.

3: Pins 1, 23 and 34 (44-PLCC) package are NC “No Internal connection”.

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