TPS54341_15 datasheet(20/48 Pages) TI

20 / 48 page

( )

OUT sc

DIV

SW(shift)

DS on

(

)

( )

OUT

SW max skip

DS on

TPS54341

SLVSC61 – NOVEMBER 2013

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DETAILED DESCRIPTION (continued)

(12)

(13)

where (for Equation 12 and Equation 13)

•

IO = output current

•

ICL = current limit

•

Rdc = inductor resistance

•

VIN = maximum input voltage

•

VOUT = output voltage

•

VOUT(SC) = output voltage during short

•

Vd = diode voltage drop

•

RDS(on) = switch on resistance

•

tON = controllable on time

•

ƒDIV, frequency divide equals (1, 2, 4, or 8)

Synchronization to RT/CLK Pin

The RT/CLK pin can receive a frequency synchronization signal from an external system clock. To implement

this synchronization feature connect a square wave to the RT/CLK pin through either circuit network shown in

Figure 38. The square wave applied to the RT/CLK pin must switch lower than 0.5 V and higher than 2 V, and

must have a pulsewidth greater than 15 ns. The synchronization frequency range is 160 to 2300 kHz. The rising

edge of the SW synchronizes to the falling edge of RT/CLK pin signal. Design the external synchronization circuit

such that the default-frequency set resistor connects from the RT/CLK pin to ground when the synchronization

signal is off. When using a low-impedance signal source, the frequency-set resistor connects in parallel with an

AC-coupling capacitor to a termination resistor (for example, 50

Ω) as shown in Figure 38. The two resistors in

the series provide the default frequency-setting resistance when the signal source is turned off. The sum of the

resistance sets the switching frequency close to the external CLK frequency. AC-coupling the synchronization

signal the synchronization signal through a 10-pF ceramic capacitor to RT/CLK pin is recommended.

The first time the RT/CLK pulls above the PLL threshold the TPS54341 device switches from the RT-resistor

free-running frequency mode to the PLL-synchronized mode. The internal 0.5-V voltage source is removed and

the RT/CLK pin becomes high impedance as the PLL begins to lock onto the external signal. The switching

frequency can be higher or lower than the frequency set with the RT/CLK resistor. The device transitions from

the resistor mode to the PLL mode and locks onto the external clock frequency within 78 µs. During the transition

from the PLL mode to the resistor-programmed mode, the switching frequency falls to 150 kHz and then

increases or decreases to the resistor-programmed frequency when the 0.5-V bias voltage is reapplied to the

RT/CLK resistor.

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