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TPS54341 数据表(PDF) 21 Page - Texas Instruments |
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TPS54341 数据表(HTML) 21 Page - Texas Instruments |
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21 / 48 page ![]() RT/CLK TPS54341 Clock Source PLL RT RT/CLK TPS54341 Hi-Z Clock Source PLL RT TPS54341 www.ti.com SLVSC61 – NOVEMBER 2013 DETAILED DESCRIPTION (continued) The switching frequency is divided by 8, 4, 2, and 1 as the FB pin voltage ramps from 0 to 0.8 V. The device implements a digital frequency foldback which enables synchronization to an external clock during normal startup and fault conditions. Figure 39, Figure 40 and Figure 41 show the device synchronized to an external system clock in continuous conduction mode (CCM), discontinuous conduction (DCM), and pulse skip mode (Eco-Mode). Figure 38. Synchronizing to a System Clock Figure 39. Plot of Synchronizing in CCM Figure 40. Plot of Synchronizing in DCM Figure 41. Plot of Synchronizing in Eco-mode Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 21 Product Folder Links: TPS54341 |
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