ML4827CS-2 datasheet(11/16 Pages) MICRO-LINEAR

11 / 16 page

ML4827

voltage for which the PWM output transistor must be

rated. Frequently, the design of the tranformer’s reset

winding, and/or of the output transistor’s snubbers or

clamps, require an additional voltage margin of 100V to

200V.

To put some numbers into the discussion, with a given

VBUSS(MAX) of 400V:

1. For

δ = 50%: VRESET = {[(1/fPWM) x δ]/[(1/fPWM) x

(1–

δ)]} x 400V = 0.50/0.50 x 400V = 400V

2. For

δ = 55%: VRESET = 0.55/0.45 x 400V = 489V

3. For

δ = 60%: VRESET = 0.60/0.40 x 400V = 600V

4. For

δ = 64% (Data Sheet Lower Limit Value): VRESET =

0.64/0.36 x 400V = 711V

5. For

δ = 70%: VRESET = 0.70/0.30 x 400V = 933V

6. For

δ = 74% (Data Sheet Upper Limit Value): VRESET =

0.74/0.26 x 400V = 1138V

It is economically desirable to design for the lowest

meaningful voltage on the output MOSFET. It is

simultaneously necessary to design the circuit to operate

FUNCTIONAL DESCRIPTION (Continued)

at the lowest guaranteed value for

δ, to ensure that the

magnetics will deliver full output power with any

individual ML4827. In actual operation, the choice of

δMIN = 60% will allow some tolerance for the timing

capacitors and resistors. A tolerance on (RRAMP2 x

CRAMP2) of ±2% is the simplest “brute force” way to

achieve the desired result. This should be combined with

an external duty cycle clamp. This protects the PWM

circuitry against the condition in which the output has

been shorted, and the error amplifier output (VDC) would

otherwise be driven to its upper rail. One method which

works well when the PWM is used in voltage mode is to

limit the maximum input to the PWM feedback voltage

(VDC). If the voltage available to this pin is derived from

the ML4827’s 7.5V VREF, it will be in close ratio to the

charging time of the RAMP2 capacitor. This will be true

whether the RAMP2 capacitor is charged from VREF, or, as

is more commonly done in voltage-mode applications,

from the output of the PFC Stage (the “feedforward”

configuration). Figure 3 shows such a duty cycle clamp.

If the ML4827-2’s PWM is to be used in a current-mode

design, the PWM stage will require slope compensation.

This can be done by any of the standard industry

techniques. Note that the ramp to use for this slope

compensation is the voltage on RAMP1.

RAMP2

VDC

VFB

PFC VBUSS

RFB1

RRAMP2

CRAMP2

RFB2

PWM

ERROR

AMP

VREF

δMAX =

VRAMP2 (PEAK)

R2 VREF

R1 + R2

Figure 3. ML4827- PWM Duty Cycle Clamp for Voltage-Made Operation

ML4827CS-2 数据表(PDF) 11 Page - Micro Linear Corporation

ML4827CS-2 数据表(HTML) 11 Page - Micro Linear Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

数据表下载