ML4827

13

The ML4827 should be locally bypassed with a 10nF and

a 1

µF ceramic capacitor. In most applications, an

electrolytic capacitor of between 100

µF and 330µF is also

required across the part, both for filtering and as part of

the start-up bootstrap circuitry.

LEADING/TRAILING MODULATION

Conventional Pulse Width Modulation (PWM) techniques

employ trailing edge modulation in which the switch will

turn on right after the trailing edge of the system clock.

The error amplifier output voltage is then compared with

the modulating ramp. When the modulating ramp reaches

the level of the error amplifier output voltage, the switch

will be turned OFF. When the switch is ON, the inductor

current will ramp up. The effective duty cycle of the

trailing edge modulation is determined during the ON

time of the switch. Figure 5 shows a typical trailing edge

control scheme.

In the case of leading edge modulation, the switch is

turned OFF right at the leading edge of the system clock.

When the modulating ramp reaches the level of the error

amplifier output voltage, the switch will be turned ON.

The effective duty-cycle of the leading edge modulation

is determined during the OFF time of the switch. Figure 6

shows a leading edge control scheme.

One of the advantages of this control technique is that it

requires only one system clock. Switch 1 (SW1) turns off

and switch 2 (SW2) turns on at the same instant to

minimize the momentary “no-load” period, thus lowering

ripple voltage generated by the switching action. With

Figure 6. Typical Leading Edge Control Scheme.

Figure 5. Typical Trailing Edge Control Scheme.

RAMP

VEAO

TIME

VSW1

TIME

REF

EA

–

+

–

+

OSC

DFF

R

D

Q

Q

CLK

U1

RAMP

CLK

U4

U3

C1

RL

I4

SW2

SW1

+

DC

I1

I2

I3

VIN

L1

U2

REF

EA

–

+

–

+

OSC

DFF

R

D

Q

Q

CLK

U1

RAMP

CLK

U4

U3

C1

RL

I4

SW2

SW1

+

DC

I1

I2

I3

VIN

L1

VEAO

CMP

U2

RAMP

VEAO

TIME

VSW1

TIME