ML4826

9

Error Amplifier Compensation

The PWM loading of the PFC can be modeled as a

negative resistor; an increase in input voltage to the PWM

causes a decrease in the input current. This response

dictates the proper compensation of the two

transconductance error amplifiers. Figure 3 shows the

types of compensation networks most commonly used for

the voltage and current error amplifiers, along with their

respective return points. The current loop compensation

the PFC: as the reference voltage comes up from zero

volts, it creates a differentiated voltage on IEAO which

prevents the PFC from immediately demanding a full duty

cycle on its boost converter.

There are two major concerns when compensating the

voltage loop error amplifier; stability and transient

response. Optimizing interaction between transient

response and stability requires that the error amplifier’s

open-loop crossover frequency should be 1/2 that of the

line frequency, or 23Hz for a 47Hz line (lowest

anticipated international power frequency). The gain vs.

input voltage of the ML4826’s voltage error amplifier has a

specially shaped nonlinearity such that under steady-state

operating conditions the transconductance of the error

amplifier is at a local minimum. Rapid perturbations in

line or load conditions will cause the input to the voltage

value. If this happens, the transconductance of the voltage

error amplifier will increase significantly, as shown in the

Typical Performance Characteristics. This increases the

gain-bandwidth product of the voltage loop, resulting in a

much more rapid voltage loop response to such

perturbations than would occur with a conventional linear

gain characteristic.

The current amplifier compensation is similar to that of the

voltage error amplifier with the exception of the choice of

crossover frequency. The crossover frequency of the

current amplifier should be at least 10 times that of the

voltage amplifier, to prevent interaction with the voltage

loop. It should also be limited to less than 1/6th that of the

switching frequency, e.g. 16.7kHz for a 100kHz switching

frequency.

For more information on compensating the current and

voltage control loops, see Application Notes 33 and 34.

Application Note 16 also contains valuable information

for the design of this class of PFC.

oscillator output clock:

f

tt

OSC

RAMP

DEADTIME

=

+

1

(2)

The deadtime of the oscillator is derived from the

following equation:

t

V

mA

CC

DEADTIME

T

T

=×

=

×

25

51

490

.

.

(3)

tC

R

RAMP

T

T

=×

× 051

.

The ramp of the oscillator may be determined using:

tC

R

In

V

V

RAMP

T

T

REF

REF

=×

×









–.

–.

125

375

(4)

operating frequency can typically be approximated by:

f

t

OSC

RAMP

=

1

(5)

For proper reset of internal circuits during dead time,

EXAMPLE:

For the application circuit shown in the data sheet, with

the oscillator running at:

f

kHz

t

OSC

RAMP

==

200

1

tC

R

RAMP

T

T

=×

×

.

The deadtime of the oscillator adds to the Maximum

PWM Duty Cycle (it is an input to the Duty Cycle Limiter).

With zero oscillator deadtime, the Maximum PWM Duty

Cycle is typically 45%. In many applications, care should

Maximum Duty Cycle beyond 50%.