ML4841

9

the voltage and current error amplifiers, along with their

respective return points. The current loop compensation

the PFC: as the reference voltage comes up from zero

volts, it creates a differentiated voltage on IEAO which

prevents the PFC from immediately demanding a full duty

cycle on its boost converter.

There are two major concerns when compensating the

voltage loop error amplifier; stability and transient

response. Optimizing interaction between transient

response and stability requires that the error amplifier’s

open-loop crossover frequency should be 1/2 that of the

line frequency, or 23Hz for a 47Hz line (lowest

anticipated international power frequency). The gain vs.

input voltage of the ML4841’s voltage error amplifier has a

specially shaped nonlinearity such that under steady-state

operating conditions the transconductance of the error

amplifier is at a local minimum. Rapid perturbations in

line or load conditions will cause the input to the voltage

value. If this happens, the transconductance of the voltage

error amplifier will increase significantly, as shown in the

Typical Performance Characteristics. This increases the

gain-bandwidth product of the voltage loop, resulting in a

much more rapid voltage loop response to such

perturbations than would occur with a conventional linear

gain characteristic.

The current amplifier compensation is similar to that of the

voltage error amplifier with the exception of the choice of

crossover frequency. The crossover frequency of the

current amplifier should be at least 10 times that of the

voltage amplifier, to prevent interaction with the voltage

loop. It should also be limited to less than 1/6th that of the

switching frequency, e.g. 16.7kHz for a 100kHz switching

frequency.

For more information on compensating the current and

voltage control loops, see Application Notes 33 and 34.

Application Note 16 also contains valuable information for

the design of this class of PFC.

oscillator output clock:

f

tt

OSC

RAMP

DISCHARGE

=

+

1

(2)

The ramp-charge time of the oscillator is derived from the

following equation:

tC

R

In

V

V

RAMP

T

T

REF

REF

=×

×

−

−









125

375

.

.

(3)

tC

R

RAMP

T

T

=×

× 051

.

The discharge time of the oscillator may be determined

using:

t

V

mA

CC

DISCHARGE

T

T

=×

=

×

25

51

490

.

.

(4)

operating frequency can typically be approximated by:

f

t

OSC

RAMP

=

1

(5)

EXAMPLE:

For the application circuit shown in the data sheet, with

the oscillator running at:

f

kHz

t

OSC

RAMP

==

200

1

tR

C

RAMP

T

T

=×

×

051

.

RAMP 1

The ramp voltage on this pin serves as a reference to

which the PFC’s current error amp output is compared in

order to set the duty cycle of the PFC switch. The external

ramp voltage is derived from a RC network similar to the

oscillator’s. The PWM’s oscillator sends a synchronous

pulse every other cycle to reset this ramp.

The ramp voltage should be limited to no more than the

output high voltage (6V) of the current error amplifier. The

timing resistor value should be selected such that the

capacitor will not charge past this point before being reset.

In order to ensure the linearity of the PFC loop’s transfer

function and improve noise immunity, the charging

the 7.5V reference. This will keep the charging voltage

across the timing cap in the “linear” region of the charging

curve.

The component value selection is similar to oscillator RC

component selection.

f

tt

OSC

CHARGE

DISCHARGE

=

+

1

(6)

The charge time of Ramp 1 is derived from the following

equations:

t

f

CHARGE

OSC

= 2

(7)

tC

R

In

V

Ramp Valley

V

Ramp Peak

CHARGE

T

T

CC

CC

=×

×

−

−









(8)